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k61p143m120sf3 k61 sub-family supports the following: MK61FN1M0CAA12 key features ? operating characteristics C voltage range: 1.71 to 3.6 v C flash write voltage range: 1.71 to 3.6 v C temperature range (ambient): -40 to 85c ? performance C up to 120 mhz arm? cortex?-m4 core with dsp instructions delivering 1.25 dhrystone mips per mhz ? memories and memory interfaces C up to 1024 kb program flash memory on non- flexmemory devices C up to 128 kb ram C serial programming interface (ezport) C flexbus external bus interface C nand flash controller interface ? clocks C 3 to 32 mhz crystal oscillator C 32 khz crystal oscillator C multi-purpose clock generator ? system peripherals C multiple low-power modes to provide power optimization based on application requirements C memory protection unit with multi-master protection C 32-channel dma controller, supporting up to 128 request sources C external watchdog monitor C software watchdog C low-leakage wakeup unit ? security and integrity modules C hardware crc module to support fast cyclic redundancy checks C tamper detect and secure storage C hardware random-number generator C hardware encryption supporting des, 3des, aes, md5, sha-1, and sha-256 algorithms C 128-bit unique identification (id) number per chip ? human-machine interface C low-power hardware touch sensor interface (tsi) C general-purpose input/output ? analog modules C four 16-bit sar adcs C programmable gain amplifier (pga) (up to x64) integrated into each adc C two 12-bit dacs C four analog comparators (cmp) containing a 6-bit dac and programmable reference input C voltage reference ? timers C programmable delay block C two 8-channel motor control/general purpose/pwm timers C two 2-channel quadrature decoder/general purpose timers C ieee 1588 timers C periodic interrupt timers C 16-bit low-power timer C carrier modulator transmitter C real-time clock ? communication interfaces C ethernet controller with mii and rmii interface to external phy and hardware ieee 1588 capability C usb high-/full-/low-speed on-the-go controller with ulpi interface C usb full-/low-speed on-the-go controller with on- chip transceiver C usb device charger detect (usbdcd) C two controller area network (can) modules C three spi modules C two i2c modules C six uart modules C secure digital host controller (sdhc) C two i2s modules nxp semiconductors document number k61p143m120sf3 data sheet: technical data rev. 7, 02/2018 nxp reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.
table of contents 1 ordering parts....................................................................................... 3 1.1 determining valid orderable parts............................................... 3 2 part identification................................................................................. 3 2.1 description................................................................................... 3 2.2 format.......................................................................................... 3 2.3 fields............................................................................................ 3 2.4 example....................................................................................... 4 3 terminology and guidelines................................................................. 4 3.1 definitions................................................................................... 4 3.2 examples...................................................................................... 4 3.3 typical-value conditions.............................................................. 5 3.4 relationship between ratings and operating requirements.......... 5 3.5 guidelines for ratings and operating requirements...................... 6 4 ratings.................................................................................................. 6 4.1 thermal handling ratings............................................................. 6 4.2 moisture handling ratings............................................................ 7 4.3 esd handling ratings................................................................... 7 4.4 voltage and current operating ratings.......................................... 7 5 general................................................................................................. 8 5.1 ac electrical characteristics........................................................ 8 5.2 nonswitching electrical specifications........................................ 8 5.2.1 voltage and current operating requirements............... 8 5.2.2 lvd and por operating requirements....................... 9 5.2.3 voltage and current operating behaviors..................... 10 5.2.4 power mode transition operating behaviors................ 13 5.2.5 power consumption operating behaviors..................... 14 5.2.6 emc radiated emissions operating behaviors............. 17 5.2.7 designing with radiated emissions in mind................. 18 5.2.8 capacitance attributes.................................................. 18 5.3 switching specifications.............................................................. 18 5.3.1 device clock specifications......................................... 18 5.3.2 general switching specifications................................. 19 5.4 thermal specifications................................................................. 20 5.4.1 thermal operating requirements.................................. 21 5.4.2 thermal attributes........................................................ 21 6 peripheral operating requirements and behaviors................................ 22 6.1 core modules............................................................................... 22 6.1.1 debug trace timing specifications............................... 22 6.1.2 jtag electricals.......................................................... 22 6.2 system modules........................................................................... 25 6.3 clock modules............................................................................. 25 6.3.1 mcg specifications..................................................... 25 6.3.2 oscillator electrical specifications............................... 28 6.3.3 32 khz oscillator electrical characteristics.................. 30 6.4 memories and memory interfaces................................................ 30 6.4.1 flash (ftfe) electrical specifications......................... 30 6.4.2 ezport switching specifications................................... 32 6.4.3 nand flash controller specifications......................... 33 6.4.4 flexbus switching specifications................................. 36 6.5 security and integrity modules.................................................... 39 6.5.1 dryice tamper electrical specifications..................... 39 6.6 analog.......................................................................................... 40 6.6.1 adc electrical specifications...................................... 40 6.6.2 cmp and 6-bit dac electrical specifications............. 47 6.6.3 12-bit dac electrical characteristics........................... 49 6.6.4 voltage reference electrical specifications.................. 52 6.7 timers.......................................................................................... 53 6.8 communication interfaces........................................................... 53 6.8.1 ethernet switching specifications................................ 53 6.8.2 usb electrical specifications....................................... 56 6.8.3 usb dcd electrical specifications............................. 56 6.8.4 usb vreg electrical specifications........................... 57 6.8.5 can switching specifications..................................... 57 6.8.6 dspi switching specifications (limited voltage range)........................................................................... 57 6.8.7 dspi switching specifications (full voltage range)..... 59 6.8.8 inter-integrated circuit interface (i2c) timing............ 61 6.8.9 uart switching specifications................................... 62 6.8.10 sdhc specifications................................................... 62 6.8.11 i2s/sai switching specifications................................ 63 6.9 human-machine interfaces (hmi)............................................... 70 6.9.1 tsi electrical specifications........................................ 70 7 dimensions........................................................................................... 71 7.1 obtaining package dimensions.................................................... 71 8 pinout................................................................................................... 71 8.1 pins with active pull control after reset....................................... 71 8.2 k61 signal multiplexing and pin assignments........................... 72 8.3 k61 pinouts.................................................................................. 78 9 revision history................................................................................... 79 k61 sub-family, rev. 7, 02/2018 2 nxp semiconductors
1 ordering parts 1.1 determining valid orderable parts valid orderable part numbers are provided on the web. to determine the orderable part numbers for this device, go to nxp.com and perform a part number search for the following device numbers: pk61 and mk61 2 part identification 2.1 description part numbers for the chip have fields that identify the specific part. you can use the values of these fields to determine the specific part you have received. 2.2 format part numbers for this device have the following format: q k## a m fff t pp cc n 2.3 fields this table lists the possible values for each field in the part number (not all combinations are valid): field description values q qualification status ? m = fully qualified, general market flow ? p = prequalification k## kinetis family ? k61 a key attribute ? f = cortex-m4 w/ dsp and fpu m flash memory type ? n = program flash only ? x = program flash and flexmemory fff program flash memory size ? 512 = 512 kb ? 1m0 = 1 mb table continues on the next page... ordering parts k61 sub-family, rev. 7, 02/2018 nxp semiconductors 3
field description values t temperature range (c) ? v = C40 to 105 ? c = C40 to 85 pp package identifier ? aa = 143 wlcsp cc maximum cpu frequency (mhz) ? 12 = 120 mhz n packaging type ? r = tape and reel 2.4 example this is an example part number: MK61FN1M0CAA12 3 terminology and guidelines 3.1 definitions key terms are defined in the following table: term definition rating a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: ? operating ratings apply during operation of the chip. ? handling ratings apply when the chip is not powered. note: the likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. operating requirement a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip operating behavior a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions typical value a specified value for a technical characteristic that: ? lies within the range of values specified by the operating behavior ? is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions note: typical values are provided as design guidelines and are neither tested nor guaranteed. terminology and guidelines k61 sub-family, rev. 7, 02/2018 4 nxp semiconductors
3.2 examples operating rating : operating requirement : operating behavior that includes a typical value : example example example example 3.3 typical-value conditions typical values assume you meet the following conditions (or other conditions as specified): symbol description value unit t a ambient temperature 25 c v dd supply voltage 3.3 v terminology and guidelines k61 sub-family, rev. 7, 02/2018 nxp semiconductors 5
3.4 relationship between ratings and operating requirements C - no permanent failure - correct operation normal operating range fatal range expected permanent failure fatal range expected permanent failure operating rating (max.) operating requirement (max.) operating requirement (min.) operating rating (min.) operating (power on) degraded operating range degraded operating range C no permanent failure handling range fatal range expected permanent failure fatal range expected permanent failure handling rating (max.) handling rating (min.) handling (power off) - no permanent failure - possible decreased life - possible incorrect operation - no permanent failure - possible decreased life - possible incorrect operation 3.5 guidelines for ratings and operating requirements follow these guidelines for ratings and operating requirements: ? never exceed any of the chips ratings. ? during normal operation, dont exceed any of the chips operating requirements. ? if you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. 4 ratings 4.1 thermal handling ratings symbol description min. max. unit notes t stg storage temperature C55 150 c 1 t sdr solder temperature, lead-free 260 c 2 1. determined according to jedec standard jesd22-a103, high temperature storage life . 2. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . ratings k61 sub-family, rev. 7, 02/2018 6 nxp semiconductors
4.2 moisture handling ratings symbol description min. max. unit notes msl moisture sensitivity level 3 1 1. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . 4.3 esd handling ratings symbol description min. max. unit notes v hbm electrostatic discharge voltage, human body model -2000 +2000 v 1 v cdm electrostatic discharge voltage, charged-device model -500 +500 v 2 i lat latch-up current at ambient temperature of 105c -100 +100 ma 3 1. determined according to jedec standard jesd22-a114, electrostatic discharge (esd) sensitivity testing human body model (hbm) . 2. determined according to jedec standard jesd22-c101, field-induced charged-device model test method for electrostatic-discharge-withstand thresholds of microelectronic components . 3. determined according to jedec standard jesd78, ic latch-up test . 4.4 voltage and current operating ratings symbol description min. max. unit v dd digital supply voltage 1 C0.3 3.8 v i dd digital supply current 300 ma v dio digital input voltage (except reset, extal0/xtal0, and extal1/xtal1) 2 C0.3 5.5 v v aio analog 3 , reset, extal0/xtal0, and extal1/xtal1 input voltage C0.3 v dd + 0.3 v i d maximum current single pin limit (applies to all digital pins) C25 25 ma v dda analog supply voltage v dd C 0.3 v dd + 0.3 v v usb0_dp usb0_dp input voltage C0.3 3.63 v v usb0_dm usb0_dm input voltage C0.3 3.63 v vregin usb regulator input C0.3 6.0 v v bat rtc battery supply voltage C0.3 3.8 v 1. it applies for all port pins except tamper pins. 2. it covers digital pins except tamper pins. 3. analog pins are defined as pins that do not have an associated general purpose i/o port function. ratings k61 sub-family, rev. 7, 02/2018 nxp semiconductors 7
5 general 5.1 ac electrical characteristics unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. 80% 20% 50% v il input signal v ih fall time high low rise time midpoint1 the midpoint is v il + (v ih - v il ) / 2 figure 1. input signal measurement reference all digital i/o switching characteristics assume: 1. output pins ? have c l =30pf loads, ? are configured for fast slew rate (portx_pcrn[sre]=0), and ? are configured for high drive strength (portx_pcrn[dse]=1) 2. input pins ? have their passive filter disabled (portx_pcrn[pfe]=0) 5.2 nonswitching electrical specifications 5.2.1 voltage and current operating requirements table 1. voltage and current operating requirements symbol description min. max. unit notes v dd supply voltage 1.71 3.6 v v dda analog supply voltage 1.71 3.6 v v dd C v dda v dd -to-v dda differential voltage C0.1 0.1 v v ss C v ssa v ss -to-v ssa differential voltage C0.1 0.1 v table continues on the next page... general k61 sub-family, rev. 7, 02/2018 8 nxp semiconductors
table 1. voltage and current operating requirements (continued) symbol description min. max. unit notes v bat rtc battery supply voltage 1.71 3.6 v v ih input high voltage (digital pins except tamper pins ) ? 2.7 v v dd 3.6 v ? 1.7 v v dd 2.7 v 0.7 v dd 0.75 v dd v v v il input low voltage (digital pins except tamper pins ) ? 2.7 v v dd 3.6 v ? 1.7 v v dd 2.7 v 0.35 v dd 0.3 v dd v v v hys input hysteresis (digital pins except tamper pins ) 0.06 v dd v i icdio digital pin (except tamper pins) negative dc injection current single pin ? v in < v ss -0.3v -5 ma 1 i icaio analog 2 , extal0/xtal0, and extal1/ xtal1 pin dc injection current single pin ? v in < v ss -0.3v (negative current injection) ? v in > v dd +0.3v (positive current injection) -5 +5 ma 3 i iccont contiguous pin dc injection current regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins ? negative current injection ? positive current injection -25 +25 ma v odpu open drain pullup voltage level v dd v dd v 4 v ram v dd voltage required to retain ram 1.2 v v rfvbat v bat voltage required to retain the vbat register file v por_vbat v 1. all 5 v tolerant digital i/o pins are internally clamped to v ss through an esd protection diode. there is no diode connection to v dd . if v in is less than v dio_min , a current limiting resistor is required. if v in greater than v dio_min (=vss-0.3v) is observed, then there is no need to provide current limiting resistors at the pads. the negative dc injection current limiting resistor is calculated as r=(v dio_min -v in )/|i icdio |. 2. analog pins are defined as pins that do not have an associated general purpose i/o port function. additionally, extal and xtal are analog pins. 3. all analog pins are internally clamped to v ss and v dd through esd protection diodes. if v in is less than v aio_min or greater than v aio_max , a current limiting resistor is required. the negative dc injection current limiting resistor is calculated as r=(v aio_min -v in )/|i icaio |. the positive injection current limiting resistor is calculated as r=(v in -v aio_max )/|i icaio |. select the larger of these two calculated resistances if the pin is exposed to positive and negative injection currents. 4. open drain outputs must be pulled to vdd. general k61 sub-family, rev. 7, 02/2018 nxp semiconductors 9
5.2.2 lvd and por operating requirements table 2. lvd and por operating requirements symbol description min. typ. max. unit notes v por falling vdd por detect voltage 0.8 1.1 1.5 v v lvdh falling low-voltage detect threshold high range (lvdv=01) 2.48 2.56 2.64 v v lvw1h v lvw2h v lvw3h v lvw4h low-voltage warning thresholds high range ? level 1 falling (lvwv=00) ? level 2 falling (lvwv=01) ? level 3 falling (lvwv=10) ? level 4 falling (lvwv=11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 v v v v 1 v hysh low-voltage inhibit reset/recover hysteresis high range 80 mv v lvdl falling low-voltage detect threshold low range (lvdv=00) 1.54 1.60 1.66 v v lvw1l v lvw2l v lvw3l v lvw4l low-voltage warning thresholds low range ? level 1 falling (lvwv=00) ? level 2 falling (lvwv=01) ? level 3 falling (lvwv=10) ? level 4 falling (lvwv=11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 v v v v 1 v hysl low-voltage inhibit reset/recover hysteresis low range 60 mv v bg bandgap voltage reference 0.97 1.00 1.03 v t lpo internal low power oscillator period factory trimmed 900 1000 1100 s 1. rising thresholds are falling threshold + hysteresis voltage table 3. vbat power operating requirements symbol description min. typ. max. unit notes v por_vbat falling vbat supply por detect voltage 0.8 1.1 1.5 v 5.2.3 voltage and current operating behaviors table 4. voltage and current operating behaviors symbol description min. typ. max. unit notes v oh output high voltage high drive strength ? 2.7 v v dd 3.6 v, i oh = -9ma ? 1.71 v v dd 2.7 v, i oh = -3ma v dd C 0.5 v dd C 0.5 v v table continues on the next page... general k61 sub-family, rev. 7, 02/2018 10 nxp semiconductors
table 4. voltage and current operating behaviors (continued) symbol description min. typ. max. unit notes output high voltage low drive strength ? 2.7 v v dd 3.6 v, i oh = -2ma ? 1.71 v v dd 2.7 v, i oh = -0.6ma v dd C 0.5 v dd C 0.5 v v i oht output high current total for all ports 100 ma i oht_io60 output high current total for fast digital ports 100 ma v oh_tamper output high voltage high drive strength ? 2.7 v v bat 3.6 v, i oh = -10ma ? 1.71 v v bat 2.7 v, i oh = -3ma v bat C 0.5 v bat C 0.5 v v output high voltage low drive strength ? 2.7 v v bat 3.6 v, i oh = -2ma ? 1.71 v v bat 2.7 v, i oh = -0.6ma v bat C 0.5 v bat C 0.5 v v i oh_tamper output high current total for tamper pins 100 ma v ol output low voltage high drive strength ? 2.7 v v dd 3.6 v, i ol = 10 ma ? 1.71 v v dd 2.7 v, i ol = 5 ma 0.5 0.5 v v output low voltage low drive strength ? 2.7 v v dd 3.6 v, i ol = 2 ma ? 1.71 v v dd 2.7 v, i ol = 1 ma 0.5 0.5 v v i olt output low current total for all ports 100 ma i olt_io60 output low current total for fast digital ports 100 ma v ol_tamper output low voltage high drive strength ? 2.7 v v bat 3.6 v, i ol = 10ma ? 1.71 v v bat 2.7 v, i ol = 3ma 0.5 0.5 v v output low voltage low drive strength ? 2.7 v v bat 3.6 v, i ol = 2ma ? 1.71 v v bat 2.7 v, i ol = 0.6ma 0.5 0.5 v v i ol_tamper output low current total for tamper pins 100 ma i ina input leakage current, analog pins and digital pins configured as analog inputs ? v ss v in v dd ? all pins except extal32, xtal32, extal, xtal ? extal (pta18) and xtal (pta19) ? extal32, xtal32 0.002 0.004 0.075 0.5 1.5 10 a a a 1 , 2 i ind input leakage current, digital pins ? v ss v in v il 2 , 3 table continues on the next page... general k61 sub-family, rev. 7, 02/2018 nxp semiconductors 11
table 4. voltage and current operating behaviors (continued) symbol description min. typ. max. unit notes ? all digital pins ? v in = v dd ? all digital pins except ptd7 ? ptd7 0.002 0.002 0.004 0.5 0.5 1 a a a i ind input leakage current, digital pins ? v il < v in < v dd ? v dd = 3.6 v ? v dd = 3.0 v ? v dd = 2.5 v ? v dd = 1.7 v 18 12 8 3 26 19 13 6 a a a a 2 , 3 , 4 i ind input leakage current, digital pins ? v dd < v in < 5.5 v 1 50 a 2 , 3 z ind input impedance examples, digital pins ? v dd = 3.6 v ? v dd = 3.0 v ? v dd = 2.5 v ? v dd = 1.7 v 48 55 57 85 k k k k 2 , 5 i in_tamper input leakage current (per tamper pin) for full temperature range 1 a i in_tamper input leakage current (per tamper pin) at 25c 0.025 a r pu internal pullup resistors (except tamper pins) 20 50 k 6 r pd internal pulldown resistors (except tamper pins) 20 50 k 7 1. analog pins are defined as pins that do not have an associated general purpose i/o port function. 2. digital pins have an associated gpio port function and have 5v tolerant inputs, except extal and xtal. 3. internal pull-up/pull-down resistors disabled. 4. characterized, not tested in production. 5. examples calculated using v il relation, v dd , and max i ind : z ind =v il /i ind . this is the impedance needed to pull a high signal to a level below v il due to leakage when v il < v in < v dd . these examples assume signal source low = 0 v. see figure 2 . 6. measured at v dd supply voltage = v dd min and vinput = v ss 7. measured at v dd supply voltage = v dd min and vinput = v dd general k61 sub-family, rev. 7, 02/2018 12 nxp semiconductors
figure 2. 5 v tolerant input iind parameter 5.2.4 power mode transition operating behaviors all specifications except t por , and vllsx run recovery times in the following table assume this clock configuration: ? cpu and system clocks = 100 mhz ? bus clock = 50 mhz ? flexbus clock = 50 mhz ? flash clock = 25 mhz ? mcg mode: fei table 5. power mode transition operating behaviors symbol description min. max. unit notes t por after a por event, amount of time from the point v dd reaches 1.71 v to execution of the first instruction across the operating temperature range of the chip. ? v dd slew rate 5.7 kv/s ? v dd slew rate < 5.7 kv/s 300 1.7 v / (v dd slew rate) s 1 ? vlls1 run 160 s ? vlls2 run 114 s ? vlls3 run 114 s ? lls run 5.0 s ? vlps run 5 s ? stop run 4.8 s 1. normal boot (ftfe_fopt[lpboot]=1) general k61 sub-family, rev. 7, 02/2018 nxp semiconductors 13
5.2.5 power consumption operating behaviors table 6. power consumption operating behaviors symbol description min. typ. max. unit notes i dda analog supply current see note ma 1 i dd_run run mode current all peripheral clocks disabled, code executing from flash ? @ 1.8v ? @ 3.0v 49.28 49.08 73.85 73.93 ma ma 2 i dd_run run mode current all peripheral clocks enabled, code executing from flash ? @ 1.8v ? @ 3.0v 74.43 74.28 99.97 100.41 ma ma 3 i dd_wait wait mode high frequency current at 3.0 v all peripheral clocks disabled 34.67 58.5 ma 2 i dd_wait wait mode reduced frequency current at 3.0 v all peripheral clocks disabled 18.03 41.91 ma 4 i dd_stop stop mode current at 3.0 v ? @ C40 to 25c ? @ 70c ? @ 85c 1.25 2.93 7.08 1.62 4.39 10.74 ma ma ma i dd_vlpr very-low-power run mode current at 3.0 v all peripheral clocks disabled 1.03 4.48 ma 5 i dd_vlpr very-low-power run mode current at 3.0 v all peripheral clocks enabled 1.58 4.96 ma 5 i dd_vlpw very-low-power wait mode current at 3.0 v 0.64 4.29 ma 5 i dd_vlps very-low-power stop mode current at 3.0 v ? @ C40 to 25c ? @ 70c ? @ 85c 0.22 0.78 2.18 0.38 1.33 3.56 ma ma ma i dd_lls low leakage stop mode current at 3.0 v ? @ C40 to 25c ? @ 70c ? @ 85c 0.22 0.78 2.16 0.37 1.33 3.52 ma ma ma i dd_vlls3 very low-leakage stop mode 3 current at 3.0 v ? @ C40 to 25c ? @ 70c ? @ 85c 4.09 20.98 84.95 5.58 28.93 111.15 a a a i dd_vlls2 very low-leakage stop mode 2 current at 3.0 v table continues on the next page... general k61 sub-family, rev. 7, 02/2018 14 nxp semiconductors
table 6. power consumption operating behaviors (continued) symbol description min. typ. max. unit notes ? @ C40 to 25c ? @ 70c ? @ 85c 2.68 8.8 37.28 4.22 10.74 43.61 a a a i dd_vlls1 very low-leakage stop mode 1 current at 3.0 v ? @ C40 to 25c ? @ 70c ? @ 85c 2.46 7.04 30.68 4.02 8.99 37.04 a a a i dd_vbat average current when cpu is not accessing rtc registers at 3.0 v ? @ C40 to 25c ? @ 70c ? @ 85c 0.89 1.28 3.10 1.10 1.85 4.3 a a a 6 1. the analog supply current is the sum of the active or disabled current for each of the analog modules on the device. see each module's specification for its supply current. 2. 120 mhz core and system clock, 60 mhz bus, 30 mhz flexbus clock, and 20 mhz flash clock. mcg configured for pee mode. all peripheral clocks disabled. 3. 120 mhz core and system clock, 60 mhz bus, 30 mhz flexbus clock, and 20 mhz flash clock. mcg configured for pee mode. all peripheral clocks enabled, but peripherals are not in active operation. 4. 25 mhz core and system clock, 25 mhz bus clock, and 12.5 mhz flexbus and flash clock. mcg configured for fei mode. 5. 4 mhz core, system, 2 mhz flexbus, and 2 mhz bus clock and 0.5 mhz flash clock. mcg configured for blpe mode. all peripheral clocks disabled. 6. includes 32khz oscillator current and rtc operation. 5.2.5.1 diagram: typical idd_run operating behavior the following data was measured under these conditions: ? mcg in fbe mode for 50 mhz and lower frequencies. mcg in fee mode at greater than 50 mhz frequencies. mcg in pee mode at greater than 100 mhz frequencies. ? usb regulator disabled ? no gpios toggled ? code execution from flash with cache enabled ? for the alloff curve, all peripheral clocks are disabled except ftfe general k61 sub-family, rev. 7, 02/2018 nxp semiconductors 15
figure 3. run mode supply current vs. core frequency general k61 sub-family, rev. 7, 02/2018 16 nxp semiconductors
figure 4. vlpr mode supply current vs. core frequency 5.2.6 emc radiated emissions operating behaviors table 7. emc radiated emissions operating behaviors for 256mapbga symbol description frequency band (mhz) typ. unit notes v re1 radiated emissions voltage, band 1 0.15C50 21 dbv 1 , 2 , 3 v re2 radiated emissions voltage, band 2 50C150 24 dbv v re3 radiated emissions voltage, band 3 150C500 29 dbv v re4 radiated emissions voltage, band 4 500C1000 28 dbv 1. determined according to iec standard 61967-1, integrated circuits - measurement of electromagnetic emissions, 150 khz to 1 ghz part 1: general conditions and definitions and iec standard 61967-2, integrated circuits - measurement of electromagnetic emissions, 150 khz to 1 ghz part 2: measurement of radiated emissionstem cell and wideband tem cell method . measurements were made while the microcontroller was running basic application code. the reported emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each frequency range. 2. v dd = 3.3 v, t a = 25 c, f osc = 12 mhz (crystal), f sys = 72 mhz, f bus = 72 mhz 3. determined according to iec standard jesd78, ic latch-up test general k61 sub-family, rev. 7, 02/2018 nxp semiconductors 17
5.2.7 designing with radiated emissions in mind to find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. go to www.nxp.com . 2. perform a keyword search for emc design. 5.2.8 capacitance attributes table 8. capacitance attributes symbol description min. max. unit c in_a input capacitance: analog pins 7 pf c in_d input capacitance: digital pins 7 pf c in_d_io60 input capacitance: fast digital pins 9 pf 5.3 switching specifications 5.3.1 device clock specifications table 9. device clock specifications symbol description min. max. unit notes normal run mode f sys system and core clock 120 mhz f sys_usbfs system and core clock when full speed usb in operation 20 mhz f enet system and core clock when ethernet in operation ? 10 mbps ? 100 mbps 5 50 mhz f bus bus clock 60 mhz fb_clk flexbus clock 50 mhz f flash flash clock 25 mhz f lptmr lptmr clock 25 mhz vlpr mode 1 f sys system and core clock 4 mhz f bus bus clock 4 mhz fb_clk flexbus clock 4 mhz table continues on the next page... general k61 sub-family, rev. 7, 02/2018 18 nxp semiconductors
table 9. device clock specifications (continued) symbol description min. max. unit notes f flash flash clock 0.5 mhz f lptmr lptmr clock 4 mhz 1. the frequency limitations in vlpr mode here override any frequency specification listed in the timing specification for any other module. 5.3.2 general switching specifications these general purpose specifications apply to all pins configured for: ? gpio signaling ? other peripheral module signaling not explicitly stated elsewhere table 10. general switching specifications symbol description min. max. unit notes gpio pin interrupt pulse width (digital glitch filter disabled) synchronous path 1.5 bus clock cycles 1 , 2 gpio pin interrupt pulse width (digital glitch filter disabled, analog filter enabled) asynchronous path 100 ns 3 gpio pin interrupt pulse width (digital glitch filter disabled, analog filter disabled) asynchronous path 16 ns 3 external reset pulse width (digital glitch filter disabled) 100 ns 3 mode select ( ezp_cs) hold time after reset deassertion 2 bus clock cycles port rise and fall time (high drive strength) ? slew disabled ? 1.71 v dd 2.7v ? 2.7 v dd 3.6v ? slew enabled ? 1.71 v dd 2.7v ? 2.7 v dd 3.6v 14 8 36 24 ns ns ns ns 4 port rise and fall time (low drive strength) ? slew disabled ? 1.71 v dd 2.7v ? 2.7 v dd 3.6v ? slew enabled ? 1.71 v dd 2.7v ? 2.7 v dd 3.6v 14 8 36 24 ns ns ns ns 5 t io50 port rise and fall time (high drive strength) ? slew disabled 6 table continues on the next page... general k61 sub-family, rev. 7, 02/2018 nxp semiconductors 19
table 10. general switching specifications (continued) symbol description min. max. unit notes ? 1.71 v dd 2.7v ? 2.7 v dd 3.6v ? slew enabled ? 1.71 v dd 2.7v ? 2.7 v dd 3.6v 7 3 28 14 ns ns ns ns t io50 port rise and fall time (low drive strength) ? slew disabled ? 1.71 v dd 2.7v ? 2.7 v dd 3.6v ? slew enabled ? 1.71 v dd 2.7v ? 2.7 v dd 3.6v 18 9 48 24 ns ns ns ns -1 t io60 port rise and fall time (high drive strength) ? slew disabled ? 1.71 v dd 2.7v ? 2.7 v dd 3.6v ? slew enabled ? 1.71 v dd 2.7v ? 2.7 v dd 3.6v 6 3 28 14 ns ns ns ns 6 t io60 port rise and fall time (low drive strength) ? slew disabled ? 1.71 v dd 2.7v ? 2.7 v dd 3.6v ? slew enabled ? 1.71 v dd 2.7v ? 2.7 v dd 3.6v 18 6 48 24 ns ns ns ns -1 1. this is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. shorter pulses may or may not be recognized. in stop, vlps, lls, and vllsx modes, the synchronizer is bypassed so shorter pulses can be recognized in that case. 2. the greater synchronous and asynchronous timing must be met. 3. this is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in stop, vlps, lls, and vllsx modes. 4. 75 pf load 5. 15 pf load 6. 25 pf load 5.4 thermal specifications general k61 sub-family, rev. 7, 02/2018 20 nxp semiconductors
5.4.1 thermal operating requirements table 11. thermal operating requirements symbol description min. max. unit t j die junction temperature C40 95 c t a ambient temperature 1 C40 85 c 1. maximum t a can be exceeded only if the user ensures that t j does not exceed maximum t j . the simplest method to determine t j is: t j = t a + r ja x chip power dissipation 5.4.2 thermal attributes board type symbol description 143 wlcsp unit notes single-layer (1s) r ja thermal resistance, junction to ambient (natural convection) 77 c/w 1 , 2 four-layer (2s2p) r ja thermal resistance, junction to ambient (natural convection) 35 c/w 1 , 2 , 3 r jb thermal resistance, junction to board 10 c/w 4 r jc thermal resistance, junction to case 1.9 c/w 5 jt thermal characterization parameter, junction to package top outside center (natural convection) 2 c/w 6 1. junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. determined according to jedec standard jesd51-2, integrated circuits thermal test method environmental conditions natural convection (still air) with the single layer board horizontal. board meets jesd51-9 specification. 3. determined according to jedec standard jesd51-6, integrated circuits thermal test method environmental conditions forced convection (moving air) with the board horizontal. 4. determined according to jedec standard jesd51-8, integrated circuit thermal test method environmental conditions junction-to-board . board temperature is measured on the top surface of the board near the package. 5. determined according to method 1012.1 of mil-std 883, test method standard, microcircuits , with the cold plate temperature used for the case temperature. the value includes the thermal resistance of the interface material between the top of the package and the cold plate. general k61 sub-family, rev. 7, 02/2018 nxp semiconductors 21
6. determined according to jedec standard jesd51-2, integrated circuits thermal test method environmental conditions natural convection (still air) . 6 peripheral operating requirements and behaviors 6.1 core modules 6.1.1 debug trace timing specifications table 12. debug trace operating behaviors symbol description min. max. unit t cyc clock period frequency dependent mhz t wl low pulse width 2 ns t wh high pulse width 2 ns t r clock and data rise time 3 ns t f clock and data fall time 3 ns t s data setup 3 ns t h data hold 2 ns traceclk t r t wh t f t cyc t wl figure 5. trace_clkout specifications th ts ts th trace_clkout trace_d[3:0] figure 6. trace data specifications peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 22 nxp semiconductors
6.1.2 jtag electricals table 13. jtag limited voltage range electricals symbol description min. max. unit operating voltage 2.7 3.6 v j1 tclk frequency of operation ? boundary scan ? jtag and cjtag ? serial wire debug 0 0 0 10 25 50 mhz j2 tclk cycle period 1/j1 ns j3 tclk clock pulse width ? boundary scan ? jtag and cjtag ? serial wire debug 50 20 10 ns ns ns j4 tclk rise and fall times 3 ns j5 boundary scan input data setup time to tclk rise 20 ns j6 boundary scan input data hold time after tclk rise 2.4 ns j7 tclk low to boundary scan output data valid 25 ns j8 tclk low to boundary scan output high-z 25 ns j9 tms, tdi input data setup time to tclk rise 8 ns j10 tms, tdi input data hold time after tclk rise 1 ns j11 tclk low to tdo data valid 17 ns j12 tclk low to tdo high-z 17 ns j13 trst assert time 100 ns j14 trst setup time (negation) to tclk high 8 ns table 14. jtag full voltage range electricals symbol description min. max. unit operating voltage 1.71 3.6 v j1 tclk frequency of operation ? boundary scan ? jtag and cjtag ? serial wire debug 0 0 0 10 20 40 mhz j2 tclk cycle period 1/j1 ns j3 tclk clock pulse width ? boundary scan ? jtag and cjtag ? serial wire debug 50 25 12.5 ns ns ns j4 tclk rise and fall times 3 ns table continues on the next page... peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 nxp semiconductors 23
table 14. jtag full voltage range electricals (continued) symbol description min. max. unit j5 boundary scan input data setup time to tclk rise 20 ns j6 boundary scan input data hold time after tclk rise 2.4 ns j7 tclk low to boundary scan output data valid 25 ns j8 tclk low to boundary scan output high-z 25 ns j9 tms, tdi input data setup time to tclk rise 8 ns j10 tms, tdi input data hold time after tclk rise 1.4 ns j11 tclk low to tdo data valid 22.1 ns j12 tclk low to tdo high-z 22.1 ns j13 trst assert time 100 ns j14 trst setup time (negation) to tclk high 8 ns j2 j3 j3 j4 j4 tclk (input) figure 7. test clock input timing j7 j8 j7 j5 j6 input data valid output data valid output data valid tclk data inputs data outputs data outputs data outputs figure 8. boundary scan (jtag) timing peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 24 nxp semiconductors
j11 j12 j11 j9 j10 input data valid output data valid output data valid tclk tdi/tms tdo tdo tdo figure 9. test access port timing j14 j13 tclk trst figure 10. trst timing 6.2 system modules there are no specifications necessary for the device's system modules. 6.3 clock modules peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 nxp semiconductors 25
6.3.1 mcg specifications table 15. mcg specifications symbol description min. typ. max. unit notes f ints_ft internal reference frequency (slow clock) factory trimmed at nominal vdd and 25 c 32.768 khz f ints_t internal reference frequency (slow clock) user trimmed 31.25 38.2 khz fdco_res_t resolution of trimmed average dco output frequency at fixed voltage and temperature using sctrim and scftrim 0.3 0.6 %f dco 1 f dco_res_t resolution of trimmed average dco output frequency at fixed voltage and temperature using sctrim only 0.2 0.5 %f dco 1 f dco_t total deviation of trimmed average dco output frequency over fixed voltage and temperature range of 0C70c 4.5 %f dco 1 f intf_ft internal reference frequency (fast clock) factory trimmed at nominal vdd and 25c 4 mhz f intf_t internal reference frequency (fast clock) user trimmed at nominal vdd and 25 c 3 5 mhz f loc_low loss of external clock minimum frequency range = 00 (3/5) x f ints_t khz f loc_high loss of external clock minimum frequency range = 01, 10, or 11 (16/5) x f ints_t khz fll f fll_ref fll reference frequency range 31.25 39.0625 khz f dco dco output frequency range low range (drs=00) 640 f fll_ref 20 20.97 25 mhz 2 , 3 mid range (drs=01) 1280 f fll_ref 40 41.94 50 mhz mid-high range (drs=10) 1920 f fll_ref 60 62.91 75 mhz high range (drs=11) 2560 f fll_ref 80 83.89 100 mhz f dco_t_dmx32 dco output frequency low range (drs=00) 732 f fll_ref 23.99 mhz 4 , 5 mid range (drs=01) 1464 f fll_ref 47.97 mhz mid-high range (drs=10) 2197 f fll_ref 71.99 mhz high range (drs=11) 2929 f fll_ref 95.98 mhz j cyc_fll fll period jitter 180 ps table continues on the next page... peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 26 nxp semiconductors
table 15. mcg specifications (continued) symbol description min. typ. max. unit notes ? f vco = 48 mhz ? f vco = 98 mhz 150 t fll_acquire fll target frequency acquisition time 1 ms 6 pll0,1 f pll_ref pll reference frequency range 8 16 mhz f vcoclk_2x vco output frequency 180 360 mhz f vcoclk pll output frequency 90 180 mhz f vcoclk_90 pll quadrature output frequency 90 180 mhz i pll pll0 operating current ? vco @ 184 mhz (f osc_hi_1 = 32 mhz, f pll_ref = 8 mhz, vdiv multiplier = 23) 2.8 ma i pll pll0 operating current ? vco @ 360 mhz (f osc_hi_1 = 32 mhz, f pll_ref = 8 mhz, vdiv multiplier = 45) 4.7 ma 7 i pll pll1 operating current ? vco @ 184 mhz (f osc_hi_1 = 32 mhz, f pll_ref = 8 mhz, vdiv multiplier = 23) 2.3 ma 7 i pll pll1 operating current ? vco @ 360 mhz (f osc_hi_1 = 32 mhz, f pll_ref = 8 mhz, vdiv multiplier = 45) 3.6 ma 7 t pll_lock lock detector detection time 100 10 -6 + 1075(1/ f pll_ref ) s 8 j cyc_pll pll period jitter (rms) ? f vco = 180 mhz ? f vco = 360 mhz 100 75 ps ps 9 j acc_pll pll accumulated jitter over 1s (rms) ? f vco = 180 mhz ? f vco = 360 mhz 600 300 ps ps 10 1. this parameter is measured with the internal reference (slow clock) being used as a reference to the fll (fei clock mode). 2. these typical values listed are with the slow internal reference clock (fei) using factory trim and dmx32=0. 3. the resulting system clock frequencies should not exceed their maximum specified values. the dco frequency deviation ( f dco_t ) over voltage and temperature should be considered. 4. these typical values listed are with the slow internal reference clock (fei) using factory trim and dmx32=1. 5. the resulting clock frequency must not exceed the maximum specified clock frequency of the device. 6. this specification applies to any time the fll reference source or reference divider is changed, trim value is changed, dmx32 bit is changed, drs bits are changed, or changing from fll disabled (blpe, blpi) to fll enabled (fei, fee, fbe, fbi). if a crystal/resonator is being used as the reference, this specification assumes it is already running. 7. excludes any oscillator currents that are also consuming power while pll is in operation. 8. this specification applies to any time the pll vco divider or reference divider is changed, or changing from pll disabled (blpe, blpi) to pll enabled (pbe, pee). if a crystal/resonator is being used as the reference, this specification assumes it is already running. 9. this specification was obtained using a freescale developed pcb. pll jitter is dependent on the noise characteristics of each pcb and results will vary. 10. accumulated jitter depends on vco frequency and vdiv. peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 nxp semiconductors 27
6.3.2 oscillator electrical specifications 6.3.2.1 oscillator dc electrical specifications table 16. oscillator dc electrical specifications symbol description min. typ. max. unit notes v dd supply voltage 1.71 3.6 v i ddosc supply current low-power mode (hgo=0) ? 32 khz ? 4 mhz ? 8 mhz (range=01) ? 16 mhz ? 24 mhz ? 32 mhz 500 200 300 950 1.2 1.5 na a a a ma ma 1 i ddosc supply current high-gain mode (hgo=1) ? 32 khz ? 4 mhz ? 8 mhz (range=01) ? 16 mhz ? 24 mhz ? 32 mhz 25 400 500 2.5 3 4 a a a ma ma ma 1 c x extal load capacitance 2 , 3 c y xtal load capacitance 2 , 3 r f feedback resistor low-frequency, low-power mode (hgo=0) m 2 , 4 feedback resistor low-frequency, high-gain mode (hgo=1) 10 m feedback resistor high-frequency, low-power mode (hgo=0) m feedback resistor high-frequency, high-gain mode (hgo=1) 1 m r s series resistor low-frequency, low-power mode (hgo=0) k series resistor low-frequency, high-gain mode (hgo=1) 200 k series resistor high-frequency, low-power mode (hgo=0) k series resistor high-frequency, high-gain mode (hgo=1) 0 k table continues on the next page... peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 28 nxp semiconductors
table 16. oscillator dc electrical specifications (continued) symbol description min. typ. max. unit notes v pp 5 peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, low-power mode (hgo=0) 0.6 v peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, high-gain mode (hgo=1) v dd v peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, low-power mode (hgo=0) 0.6 v peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, high-gain mode (hgo=1) v dd v 1. v dd =3.3 v, temperature =25 c 2. see crystal or resonator manufacturer's recommendation 3. c x and c y can be provided by using either integrated capacitors or external components. 4. when low-power mode is selected, r f is integrated and must not be attached externally. 5. the extal and xtal pins should only be connected to required oscillator components and must not be connected to any other device. 6.3.2.2 oscillator frequency specifications table 17. oscillator frequency specifications symbol description min. typ. max. unit notes f osc_lo oscillator crystal or resonator frequency low- frequency mode (mcg_c2[range]=00) 32 40 khz f osc_hi_1 oscillator crystal or resonator frequency high- frequency mode (low range) (mcg_c2[range]=01) 3 8 mhz 1 f osc_hi_2 oscillator crystal or resonator frequency high frequency mode (high range) (mcg_c2[range]=1x) 8 32 mhz f ec_extal input clock frequency (external clock mode) 60 mhz 2 , 3 t dc_extal input clock duty cycle (external clock mode) 40 50 60 % t cst crystal startup time 32 khz low-frequency, low-power mode (hgo=0) 1000 ms 4 , 5 crystal startup time 32 khz low-frequency, high-gain mode (hgo=1) 500 ms crystal startup time 8 mhz high-frequency (mcg_c2[range]=01), low-power mode (hgo=0) 0.6 ms crystal startup time 8 mhz high-frequency (mcg_c2[range]=01), high-gain mode (hgo=1) 1 ms 1. frequencies less than 8 mhz are not in the pll range. 2. other frequency limits may apply when external clock is being used as a reference for the fll or pll. 3. when transitioning from fei or fbi to fbe mode, restrict the frequency of the input clock so that, when it is divided by frdiv, it remains within the limits of the dco input clock frequency. peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 nxp semiconductors 29
4. proper pc board layout procedures must be followed to achieve specifications. 5. crystal startup time is defined as the time between the oscillator being enabled and the oscinit bit in the mcg_s register being set. note the 32 khz oscillator works in low power mode by default and cannot be moved into high power/gain mode. 6.3.3 32 khz oscillator electrical characteristics 6.3.3.1 32 khz oscillator dc electrical specifications table 18. 32khz oscillator dc electrical specifications symbol description min. typ. max. unit v bat supply voltage 1.71 3.6 v r f internal feedback resistor 100 m c para parasitical capacitance of extal32 and xtal32 5 7 pf v pp 1 peak-to-peak amplitude of oscillation 0.6 v 1. when a crystal is being used with the 32 khz oscillator, the extal32 and xtal32 pins should only be connected to required oscillator components and must not be connected to any other devices. 6.3.3.2 32 khz oscillator frequency specifications table 19. 32 khz oscillator frequency specifications symbol description min. typ. max. unit notes f osc_lo oscillator crystal 32.768 khz t start crystal start-up time 1000 ms 1 v ec_extal32 externally provided input clock amplitude 700 v bat mv 2 , 3 1. proper pc board layout procedures must be followed to achieve specifications. 2. this specification is for an externally supplied clock driven to extal32 and does not apply to any other clock input. the oscillator remains enabled and xtal32 must be left unconnected. 3. the parameter specified is a peak-to-peak value and v ih and v il specifications do not apply. the voltage of the applied clock must be within the range of v ss to v bat . 6.4 memories and memory interfaces 6.4.1 flash (ftfe) electrical specifications this section describes the electrical characteristics of the ftfe module. peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 30 nxp semiconductors
6.4.1.1 flash timing specifications program and erase the following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. table 20. nvm program/erase timing specifications symbol description min. typ. max. unit notes t hvpgm8 program phrase high-voltage time 7.5 18 s t hversscr erase flash sector high-voltage time 13 113 ms 1 t hversblk128k erase flash block high-voltage time for 128 kb 104 1808 ms 1 t hversblk256k erase flash block high-voltage time for 256 kb 208 3616 ms 1 1. maximum time based on expectations at cycling end-of-life. 6.4.1.2 flash timing specifications commands table 21. flash command timing specifications symbol description min. typ. max. unit notes t rd1blk128k t rd1blk256k read 1s block execution time ? 128 kb data flash ? 256 kb program flash 256 kb data flash 0.5 1.0 ms ms t rd1sec4k read 1s section execution time (4 kb flash) 100 s 1 t pgmchk program check execution time 80 s 1 t rdrsrc read resource execution time 40 s 1 t pgm8 program phrase execution time 70 150 s t ersblk128k t ersblk256k erase flash block execution time ? 128 kb data flash ? 256 kb program flash 256 kb data flash 110 220 925 1850 ms ms 2 t ersscr erase flash sector execution time 15 115 ms 2 t pgmsec4k program section execution time (4kb flash) 20 ms t rd1alln read 1s all blocks execution time ? program flash only devices 3.4 ms t rdonce read once execution time 30 s 1 t pgmonce program once execution time 70 s t ersall erase all blocks execution time 650 5600 ms 2 t vfykey verify backdoor access key execution time 30 s 1 t swapx01 swap control execution time ? control code 0x01 200 s peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 nxp semiconductors 31
table 21. flash command timing specifications symbol description min. typ. max. unit notes t swapx02 t swapx04 t swapx08 ? control code 0x02 ? control code 0x04 ? control code 0x08 70 70 150 150 30 s s s 1. assumes 25mhz or greater flash clock frequency. 2. maximum times for erase parameters based on expectations at cycling end-of-life. 6.4.1.3 flash high voltage current behaviors table 22. flash high voltage current behaviors symbol description min. typ. max. unit i dd_pgm average current adder during high voltage flash programming operation 3.5 7.5 ma i dd_ers average current adder during high voltage flash erase operation 1.5 4.0 ma 6.4.1.4 reliability specifications table 23. nvm reliability specifications symbol description min. typ. 1 max. unit notes program flash t nvmretp10k data retention after up to 10 k cycles 5 50 years t nvmretp1k data retention after up to 1 k cycles 20 100 years n nvmcycp cycling endurance 10 k 50 k cycles 2 1. typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25c use profile. engineering bulletin eb618 does not apply to this technology. typical endurance defined in engineering bulletin eb619. 2. cycling endurance represents number of program/erase cycles at -40c t j 125c. 6.4.2 ezport switching specifications table 24. ezport switching specifications num description min. max. unit operating voltage 1.71 3.6 v ep1 ezp_ck frequency of operation (all commands except read) f sys /2 mhz ep1a ezp_ck frequency of operation (read command) f sys /8 mhz ep2 ezp_cs negation to next ezp_cs assertion 2 x t ezp_ck ns ep3 ezp_cs input valid to ezp_ck high (setup) 5 ns table continues on the next page... peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 32 nxp semiconductors
table 24. ezport switching specifications (continued) num description min. max. unit ep4 ezp_ck high to ezp_cs input invalid (hold) 5 ns ep5 ezp_d input valid to ezp_ck high (setup) 2 ns ep6 ezp_ck high to ezp_d input invalid (hold) 5 ns ep7 ezp_ck low to ezp_q output valid 16 ns ep8 ezp_ck low to ezp_q output invalid (hold) 0 ns ep9 ezp_cs negation to ezp_q tri-state 12 ns ep2 ep3 ep4 ep5 ep6 ep7 ep8 ep9 ezp_ck ezp_cs ezp_q (output) ezp_d (input) figure 11. ezport timing diagram 6.4.3 nand flash controller specifications the nand flash controller (nfc) implements the interface to standard nand flash memory devices. this section describes the timing parameters of the nfc. in the following table: ? t h is the flash clock high time and ? t l is flash clock low time, which are defined as: input clock t scaler = nfc t = h t l t + peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 nxp semiconductors 33
the scaler value is derived from the fractional divider specified in the sim's clkdiv4 register: scaler = sim_clkdiv4[nfcfrac] + 1 sim_clkdiv4[nfcdiv] + 1 in case the reciprocal of scaler is an integer, the duty cycle of nfc clock is 50%, means t h = t l . in case the reciprocal of scaler is not an integer: (1 + scaler / 2) x = l t nfc t 2 (1 C scaler / 2) x = h t nfc t 2 for example, if scaler is 0.2, then t h = t l = t nfc /2. t nfc t h t l however, if scaler is 0.667, then t l = 2/3 x t nfc and t h = 1/3 x t nfc . t nfc t h t l note the reciprocal of scaler must be a multiple of 0.5. for example, 1, 1.5, 2, 2.5, etc. table 25. nfc specifications num description min. max. unit t cls nfc_cle setup time 2t h + t l C 1 ns t clh nfc_cle hold time t h + t l C 1 ns t cs nfc_cen setup time 2t h + t l C 1 ns t ch nfc_cen hold time t h + t l ns t wp nfc_wp pulse width t l C 1 ns t als nfc_ale setup time 2t h + t l ns t alh nfc_ale hold time t h + t l ns t ds data setup time t l C 1 ns t dh data hold time t h C 1 ns t wc write cycle time t h + t l C 1 ns t wh nfc_we hold time t h C 1 ns table continues on the next page... peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 34 nxp semiconductors
table 25. nfc specifications (continued) num description min. max. unit t rr ready to nfc_re low 4t h + 3t l + 90 ns t rp nfc_re pulse width t l + 1 ns t rc read cycle time t l + t h C 1 ns t reh nfc_re high hold time t h C 1 ns t is data input setup time 11 ns tcs tchtwp tds tdh tcls tclh nfc_cle nfc_cen nfc_we nfc_ion figure 12. command latch cycle timing tcs tchtwp tds tdh tals talh address nfc_ale nfc_cen nfc_we nfc_ion figure 13. address latch cycle timing peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 nxp semiconductors 35
tcs tch twp tds tdh data data data twc twh nfc_cen nfc_we nfc_ion figure 14. write data latch cycle timing tch trp data data data trc treh tis trr nfc_cen nfc_re nfc_ion nfc_rb figure 15. read data latch cycle timing in slow mode tch trp data data data trc treh tis trr nfc_cen nfc_re nfc_ion nfc_rb figure 16. read data latch cycle timing in fast mode and edo mode 6.4.4 flexbus switching specifications all processor bus timings are synchronous; input setup/hold and output delay are given in respect to the rising edge of a reference clock, fb_clk. the fb_clk frequency may be the same as the internal system bus frequency or an integer divider of that frequency. peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 36 nxp semiconductors
the following timing numbers indicate when data is latched or driven onto the external bus, relative to the flexbus output clock (fb_clk). all other timing relationships can be derived from these values. table 26. flexbus limited voltage range switching specifications num description min. max. unit notes operating voltage 2.7 3.6 v frequency of operation fb_clk mhz fb1 clock period 20 ns fb2 address, data, and control output valid 11.5 ns 1 fb3 address, data, and control output hold 0.5 ns 1 fb4 data and fb_ta input setup 8.5 ns 2 fb5 data and fb_ta input hold 0.5 ns 2 1. specification is valid for all fb_ad[31:0], fb_be/bwe n , fb_cs n , fb_oe, fb_r/ w, fb_tbst, fb_tsiz[1:0], fb_ale, and fb_ts. 2. specification is valid for all fb_ad[31:0] and fb_ta. table 27. flexbus full voltage range switching specifications num description min. max. unit notes operating voltage 1.71 3.6 v frequency of operation fb_clk mhz fb1 clock period 1/fb_clk ns fb2 address, data, and control output valid 13.5 ns 1 fb3 address, data, and control output hold 0 ns 1 fb4 data and fb_ta input setup 13.7 ns 2 fb5 data and fb_ta input hold 0.5 ns 2 1. specification is valid for all fb_ad[31:0], fb_be/bwe n , fb_cs n , fb_oe, fb_r/ w, fb_tbst, fb_tsiz[1:0], fb_ale, and fb_ts. 2. specification is valid for all fb_ad[31:0] and fb_ta. peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 nxp semiconductors 37
address address data tsiz aa=1 aa=0 aa=1 aa=0 fb3 fb5 fb4 fb4 fb5 fb1 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_ben fb_ta fb_tsiz[1:0] fb2 read timing parameters electricals_read.svg s0 s1 s2 s3 s0 s0 s1 s2 s3 s0 figure 17. flexbus read timing diagram peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 38 nxp semiconductors
address address data tsiz aa=1 aa=0 aa=1 aa=0 fb1 fb3 fb4 fb5 fb2 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_ben fb_ta fb_tsiz[1:0] write timing parameters electricals_write.svg figure 18. flexbus write timing diagram 6.5 security and integrity modules 6.5.1 dryice tamper electrical specifications information about security-related modules is not included in this document and is available only after a nondisclosure agreement (nda) has been signed. to request an nda, please contact your local nxp sales representative. peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 nxp semiconductors 39
6.6 analog 6.6.1 adc electrical specifications the 16-bit accuracy specifications listed in table 28 and table 29 are achievable on the differential pins adcx_dp0, adcx_dm0. the adcx_dp2 and adcx_dm2 adc inputs are connected to the pga outputs and are not direct device pins. accuracy specifications for these pins are defined in table 30 and table 31 . all other adc channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 6.6.1.1 16-bit adc operating conditions table 28. 16-bit adc operating conditions symbol description conditions min. typ. 1 max. unit notes v dda supply voltage absolute 1.71 3.6 v v dda supply voltage delta to v dd (v dd C v dda ) -100 0 +100 mv 2 v ssa ground voltage delta to v ss (v ss C v ssa ) -100 0 +100 mv 2 v refh adc reference voltage high 1.13 v dda v dda v v refl adc reference voltage low v ssa v ssa v ssa v v adin input voltage ? 16-bit differential mode ? all other modes vrefl vrefl 31/32 vrefh vrefh v c adin input capacitance ? 16-bit mode ? 8-bit / 10-bit / 12-bit modes 8 4 10 5 pf r adin input series resistance 2 5 k r as analog source resistance (external) 13-bit / 12-bit modes f adck < 4 mhz 5 k 3 f adck adc conversion clock frequency 13-bit mode 1.0 18.0 mhz 4 f adck adc conversion clock frequency 16-bit mode 2.0 12.0 mhz 4 c rate adc conversion rate 13-bit modes 5 table continues on the next page... peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 40 nxp semiconductors
table 28. 16-bit adc operating conditions (continued) symbol description conditions min. typ. 1 max. unit notes no adc hardware averaging continuous conversions enabled, subsequent conversion time 20.000 818.330 ks/s c rate adc conversion rate 16-bit mode no adc hardware averaging continuous conversions enabled, subsequent conversion time 37.037 461.467 ks/s 5 1. typical values assume v dda = 3.0 v, temp = 25 c, f adck = 1.0 mhz, unless otherwise stated. typical values are for reference only, and are not tested in production. 2. dc potential difference. 3. this resistance is external to mcu. to achieve the best results, the analog source resistance must be kept as low as possible. the results in this data sheet were derived from a system that had < 8 analog source resistance. the r as /c as time constant should be kept to < 1 ns. 4. to use the maximum adc conversion clock frequency, cfg2[adhsc] must be set and cfg1[adlpc] must be clear. 5. for guidelines and examples of conversion rate calculation, download the adc calculator tool . r as v as c as z as v adin z adin r adin r adin r adin r adin c adin pad leakage input pin input pin input pin simplified input pin equivalent circuit simplified channel select circuit adc sar engine figure 19. adc input impedance equivalency diagram 6.6.1.2 16-bit adc electrical characteristics peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 nxp semiconductors 41
table 29. 16-bit adc characteristics (v refh = v dda , v refl = v ssa ) symbol description conditions 1 min. typ. 2 max. unit notes i dda_adc supply current 0.215 1.7 ma 3 f adack adc asynchronous clock source ? adlpc = 1, adhsc = 0 ? adlpc = 1, adhsc = 1 ? adlpc = 0, adhsc = 0 ? adlpc = 0, adhsc = 1 1.2 2.4 3.0 4.4 2.4 4.0 5.2 6.2 3.9 6.1 7.3 9.5 mhz mhz mhz mhz t adack = 1/ f adack sample time see reference manual chapter for sample times tue total unadjusted error ? 12-bit modes ? <12-bit modes 4 1.4 6.8 2.1 lsb 4 5 dnl differential non- linearity ? 12-bit modes ? <12-bit modes 0.7 0.2 C1.1 to +1.9 C0.3 to 0.5 lsb 4 5 inl integral non-linearity ? 12-bit modes ? <12-bit modes 1.0 0.5 C2.7 to +1.9 C0.7 to +0.5 lsb 4 5 e fs full-scale error ? 12-bit modes ? <12-bit modes C4 C1.4 C5.4 C1.8 lsb 4 v adin = v dda 5 e q quantization error ? 16-bit modes ? 13-bit modes C1 to 0 0.5 lsb 4 enob effective number of bits 16-bit differential mode ? avg = 32 ? avg = 4 16-bit single-ended mode ? avg = 32 ? avg = 4 12.8 11.9 12.2 11.4 14.5 13.8 13.9 13.1 bits bits bits bits 6 sinad signal-to-noise plus distortion see enob 6.02 enob + 1.76 db thd total harmonic distortion 16-bit differential mode ? avg = 32 16-bit single-ended mode ? avg = 32 -94 -85 db db 7 sfdr spurious free dynamic range 16-bit differential mode ? avg = 32 16-bit single-ended mode 82 78 95 90 db db 7 table continues on the next page... peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 42 nxp semiconductors
table 29. 16-bit adc characteristics (v refh = v dda , v refl = v ssa ) (continued) symbol description conditions 1 min. typ. 2 max. unit notes ? avg = 32 e il input leakage error i in r as mv i in = leakage current (refer to the mcu's voltage and current operating ratings) temp sensor slope across the full temperature range of the device 1.55 1.62 1.69 mv/c 8 v temp25 temp sensor voltage 25 c 706 716 726 mv 8 1. all accuracy numbers assume the adc is calibrated with v refh = v dda 2. typical values assume v dda = 3.0 v, temp = 25 c, f adck = 2.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 3. the adc supply current depends on the adc conversion clock speed, conversion rate and adc_cfg1[adlpc] (low power). for lowest power operation, adc_cfg1[adlpc] must be set, the adc_cfg2[adhsc] bit must be clear with 1 mhz adc conversion clock speed. 4. 1 lsb = (v refh - v refl )/2 n 5. adc conversion clock < 16 mhz, max hardware averaging (avge = %1, avgs = %11) 6. input data is 100 hz sine wave. adc conversion clock < 12 mhz. 7. input data is 1 khz sine wave. adc conversion clock < 12 mhz. 8. adc conversion clock < 3 mhz typical adc 16-bit differential enob vs adc clock 100hz, 90% fs sine input enob adc clock frequency (mhz) 15.00 14.70 14.40 14.10 13.80 13.50 13.20 12.90 12.60 12.30 12.00 1 2 3 4 5 6 7 8 9 10 1211 hardware averaging disabled averaging of 4 samples averaging of 8 samples averaging of 32 samples figure 20. typical enob vs. adc_clk for 16-bit differential mode peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 nxp semiconductors 43
typical adc 16-bit single-ended enob vs adc clock 100hz, 90% fs sine input enob adc clock frequency (mhz) 14.00 13.75 13.25 13.00 12.75 12.50 12.00 11.75 11.50 11.25 11.00 1 2 3 4 5 6 7 8 9 10 1211 averaging of 4 samples averaging of 32 samples 13.50 12.25 figure 21. typical enob vs. adc_clk for 16-bit single-ended mode 6.6.1.3 16-bit adc with pga operating conditions table 30. 16-bit adc with pga operating conditions symbol description conditions min. typ. 1 max. unit notes v dda supply voltage absolute 1.71 3.6 v v refpga pga ref voltage vref_ou t vref_ou t vref_ou t v 2 , 3 v adin input voltage v ssa v dda v v cm input common mode range v ssa v dda v r pgad differential input impedance gain = 1, 2, 4, 8 gain = 16, 32 gain = 64 128 64 32 k in+ to in- 4 r as analog source resistance 100 5 t s adc sampling time 1.25 s 6 c rate adc conversion rate 13 bit modes no adc hardware averaging continuous conversions enabled peripheral clock = 50 mhz 18.484 450 ksps 7 16 bit modes 37.037 250 ksps 8 peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 44 nxp semiconductors
table 30. 16-bit adc with pga operating conditions symbol description conditions min. typ. 1 max. unit notes no adc hardware averaging continuous conversions enabled peripheral clock = 50 mhz 1. typical values assume v dda = 3.0 v, temp = 25c, f adck = 6 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 2. adc must be configured to use the internal voltage reference (vref_out) 3. pga reference is internally connected to the vref_out pin. if the user wishes to drive vref_out with a voltage other than the output of the vref module, the vref module must be disabled. 4. for single ended configurations the input impedance of the driven input is r pgad /2 5. the analog source resistance (r as ), external to mcu, should be kept as minimum as possible. increased r as causes drop in pga gain without affecting other performances. this is not dependent on adc clock frequency. 6. the minimum sampling time is dependent on input signal frequency and adc mode of operation. a minimum of 1.25s time should be allowed for f in =4 khz at 16-bit differential mode. recommended adc setting is: adlsmp=1, adlsts=2 at 8 mhz adc clock. 7. adc clock = 18 mhz, adlsmp = 1, adlst = 00, adhsc = 1 8. adc clock = 12 mhz, adlsmp = 1, adlst = 01, adhsc = 1 6.6.1.4 16-bit adc with pga characteristics table 31. 16-bit adc with pga characteristics symbol description conditions min. typ. 1 max. unit notes i dda_pga supply current low power (adc_pga[pgalpb]=0) 420 644 a 2 i dc_pga input dc current a 3 gain =1, v refpga =1.2v, v cm =0.5v 1.54 a gain =64, v refpga =1.2v, v cm =0.1v 0.57 a g gain 4 ? pgag=0 ? pgag=1 ? pgag=2 ? pgag=3 ? pgag=4 ? pgag=5 ? pgag=6 0.95 1.9 3.8 7.6 15.2 30.0 58.8 1 2 4 8 16 31.6 63.3 1.05 2.1 4.2 8.4 16.6 33.2 67.8 r as < 100 bw input signal bandwidth ? 16-bit modes ? < 16-bit modes 4 40 khz khz psrr power supply rejection ratio gain=1 -84 db v dda = 3v 100mv, table continues on the next page... peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 nxp semiconductors 45
table 31. 16-bit adc with pga characteristics (continued) symbol description conditions min. typ. 1 max. unit notes f vdda = 50hz, 60hz cmrr common mode rejection ratio ? gain=1 ? gain=64 -84 -85 db db v cm = 500mvpp, f vcm = 50hz, 100hz v ofs input offset voltage ? chopping disabled (adc_pga[pgachpb] =1) ? chopping enabled (adc_pga[pgachpb] =0) 2.4 0.2 mv mv output offset = v ofs *(gain+1) t gsw gain switching settling time 10 s 5 dg/dt gain drift over full temperature range ? gain=1 ? gain=64 6 31 10 42 ppm/c ppm/c dg/dv dda gain drift over supply voltage ? gain=1 ? gain=64 0.07 0.14 0.21 0.31 %/v %/v v dda from 1.71 to 3.6v e il input leakage error all modes i in r as mv i in = leakage current (refer to the mcu's voltage and current operating ratings) v pp,diff maximum differential input signal swing where v x = v refpga 0.583 v 6 snr signal-to-noise ratio ? gain=1 ? gain=64 80 52 90 66 db db 16-bit differential mode, average=32 thd total harmonic distortion ? gain=1 ? gain=64 85 49 100 95 db db 16-bit differential mode, average=32, f in =100hz sfdr spurious free dynamic range ? gain=1 ? gain=64 85 53 105 88 db db 16-bit differential mode, average=32, f in =100hz enob effective number of bits ? gain=1, average=4 ? gain=1, average=8 ? gain=64, average=4 ? gain=64, average=8 11.6 8.0 7.2 6.3 12.8 13.4 13.6 9.6 9.6 14.5 bits bits bits bits bits 16-bit differential mode,f in =100hz table continues on the next page... peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 46 nxp semiconductors
table 31. 16-bit adc with pga characteristics (continued) symbol description conditions min. typ. 1 max. unit notes ? gain=1, average=32 ? gain=2, average=32 ? gain=4, average=32 ? gain=8, average=32 ? gain=16, average=32 ? gain=32, average=32 ? gain=64, average=32 11.0 7.9 7.3 6.8 6.8 7.5 14.3 13.8 13.1 12.5 11.5 10.6 bits bits bits bits bits bits sinad signal-to-noise plus distortion ratio see enob 6.02 enob + 1.76 db 1. typical values assume v dda =3.0v, temp=25c, f adck =6mhz unless otherwise stated. 2. this current is a pga module adder, in addition to adc conversion currents. 3. between in+ and in-. the pga draws a dc current from the input terminals. the magnitude of the dc current is a strong function of input common mode voltage (v cm ) and the pga gain. 4. gain = 2 pgag 5. after changing the pga gain setting, a minimum of 2 adc+pga conversions should be ignored. 6. limit the input signal swing so that the pga does not saturate during operation. input signal swing is dependent on the pga reference voltage and gain setting. 6.6.2 cmp and 6-bit dac electrical specifications table 32. comparator and 6-bit dac electrical specifications symbol description min. typ. max. unit v dd supply voltage 1.71 3.6 v i ddhs supply current, high-speed mode (en=1, pmode=1) 200 a i ddls supply current, low-speed mode (en=1, pmode=0) 20 a v ain analog input voltage v ss C 0.3 v dd v v aio analog input offset voltage 20 mv v h analog comparator hysteresis 1 ? cr0[hystctr] = 00 ? cr0[hystctr] = 01 ? cr0[hystctr] = 10 ? cr0[hystctr] = 11 5 10 20 30 mv mv mv mv v cmpoh output high v dd C 0.5 v v cmpol output low 0.5 v t dhs propagation delay, high-speed mode (en=1, pmode=1) 20 50 200 ns t dls propagation delay, low-speed mode (en=1, pmode=0) 80 250 600 ns analog comparator initialization delay 2 40 s i dac6b 6-bit dac current adder (enabled) 7 a table continues on the next page... peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 nxp semiconductors 47
table 32. comparator and 6-bit dac electrical specifications (continued) symbol description min. typ. max. unit inl 6-bit dac integral non-linearity C0.5 0.5 lsb 3 dnl 6-bit dac differential non-linearity C0.3 0.3 lsb 1. typical hysteresis is measured with input voltage range limited to 0.6 to v dd C0.6 v. 2. comparator initialization delay is defined as the time between software writes to change control inputs (writes to cmp_daccr[dacen], cmp_daccr[vrsel], cmp_daccr[vosel], cmp_muxcr[psel], and cmp_muxcr[msel]) and the comparator output settling to a stable level. 3. 1 lsb = v reference /64 00 01 10 hystctr setting 0.1 10 11 vin level (v) cmp hystereris (v) 3.1 2.82.5 2.2 1.91.61.3 1 0.70.4 0.05 0 0.01 0.02 0.03 0.08 0.07 0.06 0.04 figure 22. typical hysteresis vs. vin level (vdd = 3.3 v, pmode = 0) peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 48 nxp semiconductors
00 01 10 hystctr setting 10 11 0.1 3.12.82.5 2.2 1.91.61.3 1 0.70.4 0.1 0 0.02 0.04 0.06 0.18 0.14 0.12 0.08 0.16 vin level (v) cmp hysteresis (v) figure 23. typical hysteresis vs. vin level (vdd = 3.3 v, pmode = 1) 6.6.3 12-bit dac electrical characteristics 6.6.3.1 12-bit dac operating requirements table 33. 12-bit dac operating requirements symbol desciption min. max. unit notes v dda supply voltage 1.71 3.6 v v dacr reference voltage 1.13 3.6 v 1 c l output load capacitance 100 pf 2 i l output load current 1 ma 1. the dac reference can be selected to be v dda or v ref_out . 2. a small load capacitance (47 pf) can improve the bandwidth performance of the dac. peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 nxp semiconductors 49
6.6.3.2 12-bit dac operating behaviors table 34. 12-bit dac operating behaviors symbol description min. typ. max. unit notes i dda_dacl p supply current low-power mode 150 a i dda_dach p supply current high-speed mode 700 a t daclp full-scale settling time (0x080 to 0xf7f) low-power mode 100 200 s 1 t dachp full-scale settling time (0x080 to 0xf7f) high-power mode 15 30 s 1 t ccdaclp code-to-code settling time (0xbf8 to 0xc08) low-power mode and high-speed mode 0.7 1 s 1 v dacoutl dac output voltage range low high-speed mode, no load, dac set to 0x000 100 mv v dacouth dac output voltage range high high- speed mode, no load, dac set to 0xfff v dacr ?100 v dacr mv inl integral non-linearity error high speed mode 8 lsb 2 dnl differential non-linearity error v dacr > 2 v 1 lsb 3 dnl differential non-linearity error v dacr = vref_out 1 lsb 4 v offset offset error 0.4 0.8 %fsr 5 e g gain error 0.1 0.6 %fsr 5 psrr power supply rejection ratio, v dda 2.4 v 60 90 db t co temperature coefficient offset voltage 3.7 v/c 6 t ge temperature coefficient gain error 0.000421 %fsr/c rop output resistance (load = 3 k) 250 sr slew rate -80h f7fh 80h ? high power (sp hp ) ? low power (sp lp ) 1.2 0.05 1.7 0.12 v/s ct channel to channel cross talk -80 db bw 3db bandwidth ? high power (sp hp ) ? low power (sp lp ) 550 40 khz 1. settling within 1 lsb 2. the inl is measured for 0 + 100 mv to v dacr ?100 mv 3. the dnl is measured for 0 + 100 mv to v dacr ?100 mv 4. the dnl is measured for 0 + 100 mv to v dacr ?100 mv with v dda > 2.4 v 5. calculated by a best fit curve from v ss + 100 mv to v dacr ? 100 mv 6. v dda = 3.0 v, reference select set for v dda (dacx_co:dacrfs = 1), high power mode (dacx_c0:lpen = 0), dac set to 0x800, temperature range is across the full range of the device peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 50 nxp semiconductors
digital code dac12 inl (lsb) 0 500 1000 1500 2000 2500 3000 3500 4000 2 4 6 8 -2 -4 -6 -8 0 figure 24. typical inl error vs. digital code peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 nxp semiconductors 51
temperature c dac12 mid level code voltage 25 55 85 105 125 1.499 -40 1.4985 1.498 1.4975 1.497 1.4965 1.496 figure 25. offset at half scale vs. temperature 6.6.4 voltage reference electrical specifications table 35. vref full-range operating requirements symbol description min. max. unit notes v dda supply voltage 1.71 3.6 v t a temperature operating temperature range of the device c c l output load capacitance 100 nf 1 , 2 1. c l must be connected to vref_out if the vref_out functionality is being used for either an internal or external reference. 2. the load capacitance should not exceed +/-25% of the nominal specified c l value over the operating temperature range of the device. peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 52 nxp semiconductors
table 36. vref full-range operating behaviors symbol description min. typ. max. unit notes v out voltage reference output with factory trim at nominal v dda and temperature=25c 1.1915 1.195 1.1977 v 1 v out voltage reference output factory trim 1.1584 1.2376 v 1 v out voltage reference output user trim 1.193 1.197 v 1 v step voltage reference trim step 0.5 mv 1 v tdrift temperature drift (vmax -vmin across the full temperature range: -40 to 85c) 70 mv 1 i bg bandgap only current 80 a 1 i hp high-power buffer current 1 ma 1 v load load regulation ? current = + 1.0 ma ? current = - 1.0 ma 2 5 mv 1 , 2 t stup buffer startup time 100 s v vdrift voltage drift (vmax -vmin across the full voltage range) 2 mv 1 1. see the chip's reference manual for the appropriate settings of the vref status and control register. 2. load regulation voltage is the difference between the vref_out voltage with no load vs. voltage with defined load table 37. vref limited-range operating requirements symbol description min. max. unit notes t a temperature 0 50 c table 38. vref limited-range operating behaviors symbol description min. max. unit notes v out voltage reference output with factory trim 1.173 1.225 v 6.7 timers see general switching specifications . 6.8 communication interfaces peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 nxp semiconductors 53
6.8.1 ethernet switching specifications the following timing specs are defined at the chip i/o pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. 6.8.1.1 mii signal switching specifications the following timing specs meet the requirements for mii style interfaces for a range of transceiver devices. table 39. mii signal switching specifications symbol description min. max. unit rxclk frequency 25 mhz mii1 rxclk pulse width high 35% 65% rxclk period mii2 rxclk pulse width low 35% 65% rxclk period mii3 rxd[3:0], rxdv, rxer to rxclk setup 5 ns mii4 rxclk to rxd[3:0], rxdv, rxer hold 5 ns txclk frequency 25 mhz mii5 txclk pulse width high 35% 65% txclk period mii6 txclk pulse width low 35% 65% txclk period mii7 txclk to txd[3:0], txen, txer invalid 2 ns mii8 txclk to txd[3:0], txen, txer valid 25 ns mii7mii8 valid data valid data valid data mii6 mii5 txclk (input) txd[n:0] txen txer figure 26. rmii/mii transmit signal timing diagram peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 54 nxp semiconductors
mii2 mii1 mii4mii3 valid data valid data valid data rxclk (input) rxd[n:0] rxdv rxer figure 27. rmii/mii receive signal timing diagram 6.8.1.2 rmii signal switching specifications the following timing specs meet the requirements for rmii style interfaces for a range of transceiver devices. table 40. rmii signal switching specifications num description min. max. unit extal frequency (rmii input clock rmii_clk) 50 mhz rmii1 rmii_clk pulse width high 35% 65% rmii_clk period rmii2 rmii_clk pulse width low 35% 65% rmii_clk period rmii3 rxd[1:0], crs_dv, rxer to rmii_clk setup 4 ns rmii4 rmii_clk to rxd[1:0], crs_dv, rxer hold 2 ns rmii7 rmii_clk to txd[1:0], txen invalid 4 ns rmii8 rmii_clk to txd[1:0], txen valid 15 ns 6.8.1.3 mdio serial management timing specifications table 41. mdio serial management channel signal timing num characteristic min max unit e10 mdc cycle time 400 ns e11 mdc pulse width 40 60 % t mdc e12 mdc to mdio output valid fsys period 1 ns e13 mdc to mdio output invalid fsys period 1 ns e14 mdio input to mdc setup 10 ns e15 mdio input to mdc hold 0 ns peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 nxp semiconductors 55
1. mdio output valid and hold time can be adjusted using the enet_mscr[holdtime] field. the minimum specification shown here is for the default enet_mscr value, where holdtime = 0. the minimum output valid and output hold times can be increased by changing the holdtime register field e11 e10 e11 e12 valid data e13 e14 e15 valid data mdc (output) mdio (output) mdio (input) figure 28. mdio serial management channel timing diagram 6.8.2 usb electrical specifications the usb electricals for the usb on-the-go module conform to the standards documented by the universal serial bus implementers forum. for the most up-to-date standards, visit usb.org . note the mcgpllclk meets the usb jitter and signaling rate specifications for certification with the use of an external clock/ crystal for both device and host modes. the mcgfllclk does not meet the usb jitter or signaling rate specifications for certification. 6.8.3 usb dcd electrical specifications table 42. usb0 dcd electrical specifications symbol description min. typ. max. unit v dp_src usb_dp source voltage (up to 250 a) 0.5 0.7 v v lgc threshold voltage for logic high 0.8 2.0 v i dp_src usb_dp source current 7 10 13 a i dm_sink usb_dm sink current 50 100 150 a r dm_dwn d- pulldown resistance for data pin contact detect 14.25 24.8 k v dat_ref data detect voltage 0.25 0.325 0.4 v peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 56 nxp semiconductors
6.8.4 usb vreg electrical specifications table 43. usb vreg electrical specifications symbol description min. typ. 1 max. unit notes vregin input supply voltage 2.7 5.5 v i ddon quiescent current run mode, load current equal zero, input supply (vregin) > 3.6 v 125 186 a i ddstby quiescent current standby mode, load current equal zero 1.1 10 a i ddoff quiescent current shutdown mode ? vregin = 5.0 v and temperature=25 c ? across operating voltage and temperature 650 4 na a i loadrun maximum load current run mode 120 ma i loadstby maximum load current standby mode 1 ma v reg33out regulator output voltage input supply (vregin) > 3.6 v ? run mode ? standby mode 3 2.1 3.3 2.8 3.6 3.6 v v v reg33out regulator output voltage input supply (vregin) < 3.6 v, pass-through mode 2.1 3.6 v 2 c out external output capacitor 1.76 2.2 8.16 f esr external output capacitor equivalent series resistance 1 100 m i lim short circuit current 290 ma 1. typical values assume vregin = 5.0 v, temp = 25 c unless otherwise stated. 2. operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to i load . 6.8.5 can switching specifications see general switching specifications . peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 nxp semiconductors 57
6.8.6 dspi switching specifications (limited voltage range) the dma serial peripheral interface dspi provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the tables below provide dspi timing characteristics for classic dspi timing modes. refer to the dspi chapter of the reference manual for information on the modified transfer formats used for communicating with slower peripheral devices. table 44. master mode dspi timing (limited voltage range) num description min. max. unit notes operating voltage 2.7 3.6 v frequency of operation 30 mhz ds1 dspi_sck output cycle time 2 x t bus ns ds2 dspi_sck output high/low time (t sck /2) ? 2 (t sck /2) + 2 ns ds3 dspi_pcs n valid to dspi_sck delay (t bus x 2) ? 2 ns 1 ds4 dspi_sck to dspi_pcs n invalid delay (t bus x 2) ? 2 ns 2 ds5 dspi_sck to dspi_sout valid 8.5 ns ds6 dspi_sck to dspi_sout invalid ?2 ns ds7 dspi_sin to dspi_sck input setup 15 ns ds8 dspi_sck to dspi_sin input hold 0 ns 1. the delay is programmable in dspix_ctarn[pssck] and dspix_ctarn[cssck]. 2. the delay is programmable in dspix_ctarn[pasc] and dspix_ctarn[asc]. ds3 ds4 ds1 ds2 ds7 ds8 first data last data ds5 first data data last data ds6 data spi_pcsn spi_sck (cpol=0) spi_sin spi_sout figure 29. dspi classic dspi timing master mode table 45. slave mode dspi timing (limited voltage range) num description min. max. unit operating voltage 2.7 3.6 v frequency of operation 15 mhz ds9 dspi_sck input cycle time 4 x t bus ns table continues on the next page... peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 58 nxp semiconductors
table 45. slave mode dspi timing (limited voltage range) (continued) num description min. max. unit ds10 dspi_sck input high/low time (t sck /2) ? 2 (t sck /2) + 2 ns ds11 dspi_sck to dspi_sout valid 10 ns ds12 dspi_sck to dspi_sout invalid 0 ns ds13 dspi_sin to dspi_sck input setup 2 ns ds14 dspi_sck to dspi_sin input hold 7 ns ds15 dspi_ss active to dspi_sout driven 14 ns ds16 dspi_ss inactive to dspi_sout not driven 14 ns first data last data first data data last data data ds15 ds10 ds9 ds16 ds11 ds12 ds14 ds13 spi_ss spi_sck (pol=0) spi_sout spi_sin figure 30. dspi classic dspi timing slave mode 6.8.7 dspi switching specifications (full voltage range) the dma serial peripheral interface dspi provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the tables below provides dspi timing characteristics for classic spi timing modes. refer to the dspi chapter of the reference manual for information on the modified transfer formats used for communicating with slower peripheral devices. table 46. master mode dspitiming (full voltage range) num description min. max. unit notes operating voltage 1.71 3.6 v 1 frequency of operation 15 mhz ds1 dspi_sck output cycle time 4 x t bus ns ds2 dspi_sck output high/low time (t sck /2) - 4 (t sck/2) + 4 ns ds3 dspi_pcs n valid to dspi_sck delay (t bus x 2) ? 4 ns 2 table continues on the next page... peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 nxp semiconductors 59
table 46. master mode dspitiming (full voltage range) (continued) num description min. max. unit notes ds4 dspi_sck to dspi_pcs n invalid delay (t bus x 2) ? 4 ns 3 ds5 dspi_sck to dspi_sout valid 10 ns ds6 dspi_sck to dspi_sout invalid -4.5 ns ds7 dspi_sin to dspi_sck input setup 20.5 ns ds8 dspi_sck to dspi_sin input hold 0 ns 1. the dspi module can operate across the entire operating voltage for the processor, but to run across the full voltage range the maximum frequency of operation is reduced. 2. the delay is programmable in spix_ctarn[pssck] and spix_ctarn[cssck]. 3. the delay is programmable in spix_ctarn[pasc] and spix_ctarn[asc]. ds3 ds4 ds1 ds2 ds7 ds8 first data last data ds5 first data data last data ds6 data spi_pcsn spi_sck (cpol=0) spi_sin spi_sout figure 31. dspi classic spi timing master mode table 47. slave mode dspi timing (full voltage range) num description min. max. unit operating voltage 1.71 3.6 v frequency of operation 7.5 mhz ds9 dspi_sck input cycle time 8 x t bus ns ds10 dspi_sck input high/low time (t sck /2) - 4 (t sck/2) + 4 ns ds11 dspi_sck to dspi_sout valid 20 ns ds12 dspi_sck to dspi_sout invalid 0 ns ds13 dspi_sin to dspi_sck input setup 2 ns ds14 dspi_sck to dspi_sin input hold 7 ns ds15 dspi_ss active to dspi_sout driven 19 ns ds16 dspi_ss inactive to dspi_sout not driven 19 ns peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 60 nxp semiconductors
first data last data first data data last data data ds15 ds10 ds9 ds16 ds11 ds12 ds14 ds13 spi_ss spi_sck (pol=0) spi_sout spi_sin figure 32. dspi classic spi timing slave mode 6.8.8 inter-integrated circuit interface (i 2 c) timing table 48. i 2 c timing characteristic symbol standard mode fast mode unit minimum maximum minimum maximum scl clock frequency f scl 0 100 0 400 1 khz hold time (repeated) start condition. after this period, the first clock pulse is generated. t hd ; sta 4 0.6 s low period of the scl clock t low 4.7 1.25 s high period of the scl clock t high 4 0.6 s set-up time for a repeated start condition t su ; sta 4.7 0.6 s data hold time for i 2 c bus devices t hd ; dat 0 2 3.45 3 0 4 0.9 2 s data set-up time t su ; dat 250 5 100 3 , 6 ns rise time of sda and scl signals t r 1000 20 +0.1c b 7 300 ns fall time of sda and scl signals t f 300 20 +0.1c b 6 300 ns set-up time for stop condition t su ; sto 4 0.6 s bus free time between stop and start condition t buf 4.7 1.3 s pulse width of spikes that must be suppressed by the input filter t sp n/a n/a 0 50 ns 1. the maximum scl clock frequency in fast mode with maximum bus loading can only be achieved when using a pin configured for high drive across the full voltage range and when using the a pin configured for low drive with vdd 2.7 v. 2. the master mode i 2 c deasserts ack of an address byte simultaneously with the falling edge of scl. if no slaves acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the sda and scl lines. 3. the maximum thd; dat must be met only if the device does not stretch the low period (tlow) of the scl signal. 4. input signal slew = 10 ns and output load = 50 pf 5. set-up time in slave-transmitter mode is 1 ipbus clock period, if the tx fifo is empty. 6. a fast mode i 2 c bus device can be used in a standard mode i2c bus system, but the requirement t su; dat 250 ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such a peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 nxp semiconductors 61
device does stretch the low period of the scl signal, then it must output the next data bit to the sda line t rmax + t su; dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification) before the scl line is released. 7. c b = total capacitance of the one bus line in pf. ? ? sda hd; sta t hd; dat t low t su; dat t high t su; sta sr p s s t hd; sta t sp t su; sto t buf t f t r t f t r scl figure 33. timing definition for fast and standard mode devices on the i 2 c bus 6.8.9 uart switching specifications see general switching specifications . 6.8.10 sdhc specifications the following timing specs are defined at the chip i/o pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. table 49. sdhc switching specifications over a limited operating voltage range num symbol description min. max. unit operating voltage 2.7 3.6 v card input clock sd1 fpp clock frequency (low speed) 0 400 khz fpp clock frequency (sd\sdio full speed\high speed) 0 25\40 mhz fpp clock frequency (mmc full speed\high speed) 0 25\50 mhz f od clock frequency (identification mode) 0 400 khz sd2 t wl clock low time 7 ns sd3 t wh clock high time 7 ns sd4 t tlh clock rise time 3 ns sd5 t thl clock fall time 3 ns sdhc output / card inputs sdhc_cmd, sdhc_dat (reference to sdhc_clk) sd6 t od sdhc output delay (output valid) -5 6.5 ns sdhc input / card inputs sdhc_cmd, sdhc_dat (reference to sdhc_clk) sd7 t isu sdhc input setup time 5 ns sd8 t ih sdhc input hold time 0 ns peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 62 nxp semiconductors
table 50. sdhc switching specifications over the full operating voltage range num symbol description min. max. unit operating voltage 1.71 3.6 v card input clock sd1 fpp clock frequency (low speed) 0 400 khz fpp clock frequency (sd\sdio full speed\high speed) 0 25\40 mhz fpp clock frequency (mmc full speed\high speed) 0 25\50 mhz f od clock frequency (identification mode) 0 400 khz sd2 t wl clock low time 7 ns sd3 t wh clock high time 7 ns sd4 t tlh clock rise time 3 ns sd5 t thl clock fall time 3 ns sdhc output / card inputs sdhc_cmd, sdhc_dat (reference to sdhc_clk) sd6 t od sdhc output delay (output valid) -5 6.5 ns sdhc input / card inputs sdhc_cmd, sdhc_dat (reference to sdhc_clk) sd7 t isu sdhc input setup time 5 ns sd8 t ih sdhc input hold time 1.3 ns sd2sd3 sd1 sd6 sd8 sd7 sdhc_clk output sdhc_cmd output sdhc_dat[3:0] input sdhc_cmd input sdhc_dat[3:0] figure 34. sdhc timing 6.8.11 i2s/sai switching specifications this section provides the ac timing for the i2s/sai module in master mode (clocks are driven) and slave mode (clocks are input). all timing is given for noninverted serial clock polarity (tcr2[bcp] is 0, rcr2[bcp] is 0) and a noninverted frame sync (tcr4[fsp] peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 nxp semiconductors 63
is 0, rcr4[fsp] is 0). if the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the bit clock signal (bclk) and/or the frame sync (fs) signal shown in the following figures. 6.8.11.1 normal run, wait and stop mode performance over a limited operating voltage range this section provides the operating performance over a limited operating voltage for the device in normal run, wait and stop modes. table 51. i2s/sai master mode timing in normal run, wait and stop modes (limited voltage range) num. characteristic min. max. unit operating voltage 2.7 3.6 v s1 i2s_mclk cycle time 40 ns s2 i2s_mclk pulse width high/low 45% 55% mclk period s3 i2s_tx_bclk/i2s_rx_bclk cycle time (output) 80 ns s4 i2s_tx_bclk/i2s_rx_bclk pulse width high/low 45% 55% bclk period s5 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output valid 15 ns s6 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output invalid 0 ns s7 i2s_tx_bclk to i2s_txd valid 15 ns s8 i2s_tx_bclk to i2s_txd invalid 0 ns s9 i2s_rxd/i2s_rx_fs input setup before i2s_rx_bclk 15 ns s10 i2s_rxd/i2s_rx_fs input hold after i2s_rx_bclk 0 ns peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 64 nxp semiconductors
s1 s2 s2 s3 s4 s4 s5 s9 s7 s9 s10 s7 s8 s6 s10 s8 i2s_mclk (output) i2s_tx_bclk/ i2s_rx_bclk (output) i2s_tx_fs/ i2s_rx_fs (output) i2s_tx_fs/ i2s_rx_fs (input) i2s_txd i2s_rxd figure 35. i2s/sai timing master modes table 52. i2s/sai slave mode timing in normal run, wait and stop modes (limited voltage range) num. characteristic min. max. unit operating voltage 2.7 3.6 v s11 i2s_tx_bclk/i2s_rx_bclk cycle time (input) 80 ns s12 i2s_tx_bclk/i2s_rx_bclk pulse width high/low (input) 45% 55% mclk period s13 i2s_tx_fs/i2s_rx_fs input setup before i2s_tx_bclk/i2s_rx_bclk 4.5 ns s14 i2s_tx_fs/i2s_rx_fs input hold after i2s_tx_bclk/i2s_rx_bclk 2 ns s15 i2s_tx_bclk to i2s_txd/i2s_tx_fs output valid ? multiple sai synchronous mode ? all other modes 21 15 ns s16 i2s_tx_bclk to i2s_txd/i2s_tx_fs output invalid 0 ns s17 i2s_rxd setup before i2s_rx_bclk 4.5 ns s18 i2s_rxd hold after i2s_rx_bclk 2 ns s19 i2s_tx_fs input assertion to i2s_txd output valid 1 25 ns 1. applies to first bit in each frame and only if the tcr4[fse] bit is clear peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 nxp semiconductors 65
s15 s13 s15 s17 s18 s15 s16 s16 s14 s16 s11 s12 s12 i2s_tx_bclk/ i2s_rx_bclk (input) i2s_tx_fs/ i2s_rx_fs (output) i2s_txd i2s_rxd i2s_tx_fs/ i2s_rx_fs (input) s19 figure 36. i2s/sai timing slave modes 6.8.11.2 normal run, wait and stop mode performance over the full operating voltage range this section provides the operating performance over the full operating voltage for the device in normal run, wait and stop modes. table 53. i2s/sai master mode timing in normal run, wait and stop modes (full voltage range) num. characteristic min. max. unit operating voltage 1.71 3.6 v s1 i2s_mclk cycle time 40 ns s2 i2s_mclk pulse width high/low 45% 55% mclk period s3 i2s_tx_bclk/i2s_rx_bclk cycle time (output) 80 ns s4 i2s_tx_bclk/i2s_rx_bclk pulse width high/low 45% 55% bclk period s5 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output valid 15 ns s6 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output invalid -1.0 ns s7 i2s_tx_bclk to i2s_txd valid 15 ns s8 i2s_tx_bclk to i2s_txd invalid 0 ns s9 i2s_rxd/i2s_rx_fs input setup before i2s_rx_bclk 20.5 ns s10 i2s_rxd/i2s_rx_fs input hold after i2s_rx_bclk 0 ns peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 66 nxp semiconductors
s1 s2 s2 s3 s4 s4 s5 s9 s7 s9 s10 s7 s8 s6 s10 s8 i2s_mclk (output) i2s_tx_bclk/ i2s_rx_bclk (output) i2s_tx_fs/ i2s_rx_fs (output) i2s_tx_fs/ i2s_rx_fs (input) i2s_txd i2s_rxd figure 37. i2s/sai timing master modes table 54. i2s/sai slave mode timing in normal run, wait and stop modes (full voltage range) num. characteristic min. max. unit operating voltage 1.71 3.6 v s11 i2s_tx_bclk/i2s_rx_bclk cycle time (input) 80 ns s12 i2s_tx_bclk/i2s_rx_bclk pulse width high/low (input) 45% 55% mclk period s13 i2s_tx_fs/i2s_rx_fs input setup before i2s_tx_bclk/i2s_rx_bclk 5.8 ns s14 i2s_tx_fs/i2s_rx_fs input hold after i2s_tx_bclk/i2s_rx_bclk 2 ns s15 i2s_tx_bclk to i2s_txd/i2s_tx_fs output valid ? multiple sai synchronous mode ? all other modes 24 20.6 ns s16 i2s_tx_bclk to i2s_txd/i2s_tx_fs output invalid 0 ns s17 i2s_rxd setup before i2s_rx_bclk 5.8 ns s18 i2s_rxd hold after i2s_rx_bclk 2 ns s19 i2s_tx_fs input assertion to i2s_txd output valid 1 25 ns 1. applies to first bit in each frame and only if the tcr4[fse] bit is clear peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 nxp semiconductors 67
s15 s13 s15 s17 s18 s15 s16 s16 s14 s16 s11 s12 s12 i2s_tx_bclk/ i2s_rx_bclk (input) i2s_tx_fs/ i2s_rx_fs (output) i2s_txd i2s_rxd i2s_tx_fs/ i2s_rx_fs (input) s19 figure 38. i2s/sai timing slave modes 6.8.11.3 vlpr, vlpw, and vlps mode performance over the full operating voltage range this section provides the operating performance over the full operating voltage for the device in vlpr, vlpw, and vlps modes. table 55. i2s/sai master mode timing in vlpr, vlpw, and vlps modes (full voltage range) num. characteristic min. max. unit operating voltage 1.71 3.6 v s1 i2s_mclk cycle time 62.5 ns s2 i2s_mclk pulse width high/low 45% 55% mclk period s3 i2s_tx_bclk/i2s_rx_bclk cycle time (output) 250 ns s4 i2s_tx_bclk/i2s_rx_bclk pulse width high/low 45% 55% bclk period s5 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output valid 45 ns s6 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output invalid 0 ns s7 i2s_tx_bclk to i2s_txd valid 45 ns s8 i2s_tx_bclk to i2s_txd invalid -1.6 ns s9 i2s_rxd/i2s_rx_fs input setup before i2s_rx_bclk 45 ns s10 i2s_rxd/i2s_rx_fs input hold after i2s_rx_bclk 0 ns peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 68 nxp semiconductors
s1 s2 s2 s3 s4 s4 s5 s9 s7 s9 s10 s7 s8 s6 s10 s8 i2s_mclk (output) i2s_tx_bclk/ i2s_rx_bclk (output) i2s_tx_fs/ i2s_rx_fs (output) i2s_tx_fs/ i2s_rx_fs (input) i2s_txd i2s_rxd figure 39. i2s/sai timing master modes table 56. i2s/sai slave mode timing in vlpr, vlpw, and vlps modes (full voltage range) num. characteristic min. max. unit operating voltage 1.71 3.6 v s11 i2s_tx_bclk/i2s_rx_bclk cycle time (input) 250 ns s12 i2s_tx_bclk/i2s_rx_bclk pulse width high/low (input) 45% 55% mclk period s13 i2s_tx_fs/i2s_rx_fs input setup before i2s_tx_bclk/i2s_rx_bclk 30 ns s14 i2s_tx_fs/i2s_rx_fs input hold after i2s_tx_bclk/i2s_rx_bclk 3 ns s15 i2s_tx_bclk to i2s_txd/i2s_tx_fs output valid 63 ns s16 i2s_tx_bclk to i2s_txd/i2s_tx_fs output invalid 0 ns s17 i2s_rxd setup before i2s_rx_bclk 30 ns s18 i2s_rxd hold after i2s_rx_bclk 2 ns s19 i2s_tx_fs input assertion to i2s_txd output valid 1 72 ns 1. applies to first bit in each frame and only if the tcr4[fse] bit is clear peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 nxp semiconductors 69
s15 s13 s15 s17 s18 s15 s16 s16 s14 s16 s11 s12 s12 i2s_tx_bclk/ i2s_rx_bclk (input) i2s_tx_fs/ i2s_rx_fs (output) i2s_txd i2s_rxd i2s_tx_fs/ i2s_rx_fs (input) s19 figure 40. i2s/sai timing slave modes 6.9 human-machine interfaces (hmi) 6.9.1 tsi electrical specifications table 57. tsi electrical specifications symbol description min. typ. max. unit notes v ddtsi operating voltage 1.71 3.6 v c ele target electrode capacitance range 1 20 500 pf 1 f refmax reference oscillator frequency 8 15 mhz 2 , 3 f elemax electrode oscillator frequency 1 1.8 mhz 2 , 4 c ref internal reference capacitor 1 pf v delta oscillator delta voltage 600 mv 2 , 5 i ref reference oscillator current source base current ? 2 a setting (refchrg = 0) ? 32 a setting (refchrg = 15) 2 36 3 50 a 2 , 6 i ele electrode oscillator current source base current ? 2 a setting (extchrg = 0) ? 32 a setting (extchrg = 15) 2 36 3 50 a 2 , 7 pres5 electrode capacitance measurement precision 8.3333 38400 ff/count 8 pres20 electrode capacitance measurement precision 8.3333 38400 ff/count 9 pres100 electrode capacitance measurement precision 8.3333 38400 ff/count 10 maxsens maximum sensitivity 0.008 1.46 ff/count 11 res resolution 16 bits t con20 response time @ 20 pf 8 15 25 s 12 i tsi_run current added in run mode 55 a i tsi_lp low power mode current adder 1.3 2.5 a 13 peripheral operating requirements and behaviors k61 sub-family, rev. 7, 02/2018 70 nxp semiconductors
1. the tsi module is functional with capacitance values outside this range. however, optimal performance is not guaranteed. 2. fixed external capacitance of 20 pf. 3. refchrg = 2, extchrg=0. 4. refchrg = 0, extchrg = 10. 5. v dd = 3.0 v. 6. the programmable current source value is generated by multiplying the scanc[refchrg] value and the base current. 7. the programmable current source value is generated by multiplying the scanc[extchrg] value and the base current. 8. measured with a 5 pf electrode, reference oscillator frequency of 10 mhz, ps = 128, nscn = 8; iext = 16. 9. measured with a 20 pf electrode, reference oscillator frequency of 10 mhz, ps = 128, nscn = 2; iext = 16. 10. measured with a 20 pf electrode, reference oscillator frequency of 10 mhz, ps = 16, nscn = 3; iext = 16. 11. sensitivity defines the minimum capacitance change when a single count from the tsi module changes. sensitivity depends on the configuration used. the documented values are provided as examples calculated for a specific configuration of operating conditions using the following equation: (c ref * i ext )/( i ref * ps * nscn) the typical value is calculated with the following configuration: i ext = 6 a (extchrg = 2), ps = 128, nscn = 2, i ref = 16 a (refchrg = 7), c ref = 1.0 pf the minimum value is calculated with the following configuration: i ext = 2 a (extchrg = 0), ps = 128, nscn = 32, i ref = 32 a (refchrg = 15), c ref = 0.5 pf the highest possible sensitivity is the minimum value because it represents the smallest possible capacitance that can be measured by a single count. 12. time to do one complete measurement of the electrode. sensitivity resolution of 0.0133 pf, ps = 0, nscn = 0, 1 electrode, extchrg = 7. 13. refchrg=0, extchrg=4, ps=7, nscn=0f, lpscnitv=f, lpo is selected (1 khz), and fixed external capacitance of 20 pf. data is captured with an average of 7 periods window. 7 dimensions 7.1 obtaining package dimensions package dimensions are provided in package drawings. to find a package drawing, go to nxp.com and perform a keyword search for the drawings document number: if you want the drawing for this package then use this document number 143-pin wlcsp 98asa00402d 8 pinout 8.1 pins with active pull control after reset the following pins are actively pulled up or down after reset: dimensions k61 sub-family, rev. 7, 02/2018 nxp semiconductors 71
table 58. pins with active pull control after reset pin active pull direction after reset pta0 pulldown pta1 pullup pta3 pullup pta4 pullup reset_b pullup 8.2 k61 signal multiplexing and pin assignments the following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. the port control module is responsible for selecting which alt functionality is available on each pin. 143 wlc sp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport a11 pte0 adc1_se4a adc1_se4a pte0 spi1_pcs1 uart1_tx sdhc0_d1 i2c1_sda rtc_ clkout c10 pte1/ llwu_p0 adc1_se5a adc1_se5a pte1/ llwu_p0 spi1_sout uart1_rx sdhc0_d0 i2c1_scl spi1_sin b11 pte2/ llwu_p1 adc1_se6a adc1_se6a pte2/ llwu_p1 spi1_sck uart1_cts_ b sdhc0_dclk d10 pte3 adc1_se7a adc1_se7a pte3 spi1_sin uart1_rts_ b sdhc0_cmd spi1_sout e7 vdd vdd vdd e8 vss vss vss c11 pte4/ llwu_p2 disabled pte4/ llwu_p2 spi1_pcs0 uart3_tx sdhc0_d3 d11 pte5 disabled pte5 spi1_pcs2 uart3_rx sdhc0_d2 ftm3_ch0 e9 pte6 disabled pte6 spi1_pcs3 uart3_cts_ b i2s0_mclk ftm3_ch1 usb_sof_ out e10 pte7 disabled pte7 uart3_rts_ b i2s0_rxd0 ftm3_ch2 e11 pte8 adc2_se16 adc2_se16 pte8 i2s0_rxd1 uart5_tx i2s0_rx_fs ftm3_ch3 f8 pte9 adc2_se17 adc2_se17 pte9 i2s0_txd1 uart5_rx i2s0_rx_ bclk ftm3_ch4 f9 pte10 disabled pte10 uart5_cts_ b i2s0_txd0 ftm3_ch5 f10 pte11 adc3_se16 adc3_se16 pte11 uart5_rts_ b i2s0_tx_fs ftm3_ch6 f11 pte12 adc3_se17 adc3_se17 pte12 i2s0_tx_ bclk ftm3_ch7 f7 vdd vdd vdd pinout k61 sub-family, rev. 7, 02/2018 72 nxp semiconductors
143 wlc sp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport e6 vss vss vss g11 usb0_dp usb0_dp usb0_dp g10 usb0_dm usb0_dm usb0_dm g9 vout33 vout33 vout33 g8 vregin vregin vregin h11 pga2_dp/ adc2_dp0/ adc3_dp3/ adc0_dp1 pga2_dp/ adc2_dp0/ adc3_dp3/ adc0_dp1 pga2_dp/ adc2_dp0/ adc3_dp3/ adc0_dp1 h10 pga2_dm/ adc2_dm0/ adc3_dm3/ adc0_dm1 pga2_dm/ adc2_dm0/ adc3_dm3/ adc0_dm1 pga2_dm/ adc2_dm0/ adc3_dm3/ adc0_dm1 h9 pga3_dp/ adc3_dp0/ adc2_dp3/ adc1_dp1 pga3_dp/ adc3_dp0/ adc2_dp3/ adc1_dp1 pga3_dp/ adc3_dp0/ adc2_dp3/ adc1_dp1 h8 pga3_dm/ adc3_dm0/ adc2_dm3/ adc1_dm1 pga3_dm/ adc3_dm0/ adc2_dm3/ adc1_dm1 pga3_dm/ adc3_dm0/ adc2_dm3/ adc1_dm1 j11 pga0_dp/ adc0_dp0/ adc1_dp3 pga0_dp/ adc0_dp0/ adc1_dp3 pga0_dp/ adc0_dp0/ adc1_dp3 j10 pga0_dm/ adc0_dm0/ adc1_dm3 pga0_dm/ adc0_dm0/ adc1_dm3 pga0_dm/ adc0_dm0/ adc1_dm3 j9 pga1_dp/ adc1_dp0/ adc0_dp3 pga1_dp/ adc1_dp0/ adc0_dp3 pga1_dp/ adc1_dp0/ adc0_dp3 j8 pga1_dm/ adc1_dm0/ adc0_dm3 pga1_dm/ adc1_dm0/ adc0_dm3 pga1_dm/ adc1_dm0/ adc0_dm3 k11 vdda vdda vdda k10 vrefh vrefh vrefh k9 vrefl vrefl vrefl k8 vssa vssa vssa j7 vref_out/ cmp1_in5/ cmp0_in5/ adc1_se18 vref_out/ cmp1_in5/ cmp0_in5/ adc1_se18 vref_out/ cmp1_in5/ cmp0_in5/ adc1_se18 l11 dac0_out/ cmp1_in3/ adc0_se23 dac0_out/ cmp1_in3/ adc0_se23 dac0_out/ cmp1_in3/ adc0_se23 k7 dac1_out/ cmp0_in4/ cmp2_in3/ adc1_se23 dac1_out/ cmp0_in4/ cmp2_in3/ adc1_se23 dac1_out/ cmp0_in4/ cmp2_in3/ adc1_se23 pinout k61 sub-family, rev. 7, 02/2018 nxp semiconductors 73
143 wlc sp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport m11 tamper0/ rtc_ wakeup_b tamper0/ rtc_ wakeup_b tamper0/ rtc_ wakeup_b m10 tamper1 tamper1 tamper1 m9 tamper2 tamper2 tamper2 m8 tamper3 tamper3 tamper3 l10 xtal32 xtal32 xtal32 l9 extal32 extal32 extal32 l8 vbat vbat vbat l7 pte24 adc0_se17/ extal1 adc0_se17/ extal1 pte24 can1_tx uart4_tx i2s1_tx_fs ewm_out_b i2s1_rxd1 h7 pte25 adc0_se18/ xtal1 adc0_se18/ xtal1 pte25 can1_rx uart4_rx i2s1_tx_ bclk ewm_in i2s1_txd1 h6 pte26 adc3_se5b adc3_se5b pte26 enet_1588_ clkin uart4_cts_ b i2s1_txd0 rtc_ clkout usb_clkin l6 pte27 adc3_se4b adc3_se4b pte27 uart4_rts_ b i2s1_mclk k6 pta0 jtag_tclk/ swd_clk/ ezp_clk tsi0_ch1 pta0 uart0_cts_ b/ uart0_col_ b ftm0_ch5 jtag_tclk/ swd_clk ezp_clk j6 pta1 jtag_tdi/ ezp_di tsi0_ch2 pta1 uart0_rx ftm0_ch6 jtag_tdi ezp_di h5 pta2 jtag_tdo/ trace_swo/ ezp_do tsi0_ch3 pta2 uart0_tx ftm0_ch7 jtag_tdo/ trace_swo ezp_do j5 pta3 jtag_tms/ swd_dio tsi0_ch4 pta3 uart0_rts_ b ftm0_ch0 jtag_tms/ swd_dio k5 pta4/ llwu_p3 nmi_b/ ezp_cs_b tsi0_ch5 pta4/ llwu_p3 ftm0_ch1 nmi_b ezp_cs_b l5 pta5 disabled pta5 usb_clkin ftm0_ch2 rmii0_rxer/ mii0_rxer cmp2_out i2s0_tx_ bclk jtag_trst_ b g5 vdd vdd vdd f5 vss vss vss l4 pta12 cmp2_in0 cmp2_in0 pta12 can0_tx ftm1_ch0 rmii0_rxd1/ mii0_rxd1 i2s0_txd0 ftm1_qd_ pha k4 pta13/ llwu_p4 cmp2_in1 cmp2_in1 pta13/ llwu_p4 can0_rx ftm1_ch1 rmii0_rxd0/ mii0_rxd0 i2s0_tx_fs ftm1_qd_ phb j4 pta14 cmp3_in0 cmp3_in0 pta14 spi0_pcs0 uart0_tx rmii0_crs_ dv/ mii0_rxdv i2s0_rx_ bclk i2s0_txd1 l3 pta15 cmp3_in1 cmp3_in1 pta15 spi0_sck uart0_rx rmii0_txen/ mii0_txen i2s0_rxd0 k3 pta16 cmp3_in2 cmp3_in2 pta16 spi0_sout uart0_cts_ b/ uart0_col_ b rmii0_txd0/ mii0_txd0 i2s0_rx_fs i2s0_rxd1 pinout k61 sub-family, rev. 7, 02/2018 74 nxp semiconductors
143 wlc sp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport j3 pta17 adc1_se17 adc1_se17 pta17 spi0_sin uart0_rts_ b rmii0_txd1/ mii0_txd1 i2s0_mclk l2 vdd vdd vdd j2 vss vss vss l1 pta18 extal0 extal0 pta18 ftm0_flt2 ftm_clkin0 k1 pta19 xtal0 xtal0 pta19 ftm1_flt0 ftm_clkin1 lptmr0_ alt1 j1 reset_b reset_b reset_b h4 ptb0/ llwu_p5 adc0_se8/ adc1_se8/ adc2_se8/ adc3_se8/ tsi0_ch0 adc0_se8/ adc1_se8/ adc2_se8/ adc3_se8/ tsi0_ch0 ptb0/ llwu_p5 i2c0_scl ftm1_ch0 rmii0_mdio/ mii0_mdio ftm1_qd_ pha h3 ptb1 adc0_se9/ adc1_se9/ adc2_se9/ adc3_se9/ tsi0_ch6 adc0_se9/ adc1_se9/ adc2_se9/ adc3_se9/ tsi0_ch6 ptb1 i2c0_sda ftm1_ch1 rmii0_mdc/ mii0_mdc ftm1_qd_ phb h2 ptb2 adc0_se12/ tsi0_ch7 adc0_se12/ tsi0_ch7 ptb2 i2c0_scl uart0_rts_ b enet0_1588_ tmr0 ftm0_flt3 h1 ptb3 adc0_se13/ tsi0_ch8 adc0_se13/ tsi0_ch8 ptb3 i2c0_sda uart0_cts_ b/ uart0_col_ b enet0_1588_ tmr1 ftm0_flt0 g4 ptb4 adc1_se10 adc1_se10 ptb4 enet0_1588_ tmr2 ftm1_flt0 g3 ptb5 adc1_se11 adc1_se11 ptb5 enet0_1588_ tmr3 ftm2_flt0 g2 ptb6 adc1_se12 adc1_se12 ptb6 fb_ad23 g1 ptb7 adc1_se13 adc1_se13 ptb7 fb_ad22 f4 ptb8 disabled ptb8 uart3_rts_ b fb_ad21 f3 ptb9 disabled ptb9 spi1_pcs1 uart3_cts_ b fb_ad20 f2 ptb10 adc1_se14 adc1_se14 ptb10 spi1_pcs0 uart3_rx i2s1_tx_ bclk fb_ad19 ftm0_flt1 f1 ptb11 adc1_se15 adc1_se15 ptb11 spi1_sck uart3_tx i2s1_tx_fs fb_ad18 ftm0_flt2 g6 vss vss vss e5 vdd vdd vdd e1 ptb16 tsi0_ch9 tsi0_ch9 ptb16 spi1_sout uart0_rx i2s1_txd0 fb_ad17 ewm_in e2 ptb17 tsi0_ch10 tsi0_ch10 ptb17 spi1_sin uart0_tx i2s1_txd1 fb_ad16 ewm_out_b e3 ptb18 tsi0_ch11 tsi0_ch11 ptb18 can0_tx ftm2_ch0 i2s0_tx_ bclk fb_ad15 ftm2_qd_ pha e4 ptb19 tsi0_ch12 tsi0_ch12 ptb19 can0_rx ftm2_ch1 i2s0_tx_fs fb_oe_b ftm2_qd_ phb d1 ptb20 adc2_se4a adc2_se4a ptb20 spi2_pcs0 fb_ad31/ nfc_data15 cmp0_out pinout k61 sub-family, rev. 7, 02/2018 nxp semiconductors 75
143 wlc sp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport d2 ptb21 adc2_se5a adc2_se5a ptb21 spi2_sck fb_ad30/ nfc_data14 cmp1_out d5 ptb22 disabled ptb22 spi2_sout fb_ad29/ nfc_data13 cmp2_out d4 ptb23 disabled ptb23 spi2_sin spi0_pcs5 fb_ad28/ nfc_data12 cmp3_out d3 ptc0 adc0_se14/ tsi0_ch13 adc0_se14/ tsi0_ch13 ptc0 spi0_pcs4 pdb0_extrg fb_ad14/ nfc_data11 i2s0_txd1 c1 ptc1/ llwu_p6 adc0_se15/ tsi0_ch14 adc0_se15/ tsi0_ch14 ptc1/ llwu_p6 spi0_pcs3 uart1_rts_ b ftm0_ch0 fb_ad13/ nfc_data10 i2s0_txd0 c2 ptc2 adc0_se4b/ cmp1_in0/ tsi0_ch15 adc0_se4b/ cmp1_in0/ tsi0_ch15 ptc2 spi0_pcs2 uart1_cts_ b ftm0_ch1 fb_ad12/ nfc_data9 i2s0_tx_fs b1 ptc3/ llwu_p7 cmp1_in1 cmp1_in1 ptc3/ llwu_p7 spi0_pcs1 uart1_rx ftm0_ch2 clkout i2s0_tx_ bclk g7 vdd vdd vdd a3 ptc4/ llwu_p8 disabled ptc4/ llwu_p8 spi0_pcs0 uart1_tx ftm0_ch3 fb_ad11/ nfc_data8 cmp1_out i2s1_tx_ bclk b4 ptc5/ llwu_p9 disabled ptc5/ llwu_p9 spi0_sck lptmr0_ alt2 i2s0_rxd0 fb_ad10/ nfc_data7 cmp0_out i2s1_tx_fs c5 ptc6/ llwu_p10 cmp0_in0 cmp0_in0 ptc6/ llwu_p10 spi0_sout pdb0_extrg i2s0_rx_ bclk fb_ad9/ nfc_data6 i2s0_mclk b5 ptc7 cmp0_in1 cmp0_in1 ptc7 spi0_sin usb_sof_ out i2s0_rx_fs fb_ad8/ nfc_data5 a4 ptc8 adc1_se4b/ cmp0_in2 adc1_se4b/ cmp0_in2 ptc8 ftm3_ch4 i2s0_mclk fb_ad7/ nfc_data4 c6 ptc9 adc1_se5b/ cmp0_in3 adc1_se5b/ cmp0_in3 ptc9 ftm3_ch5 i2s0_rx_ bclk fb_ad6/ nfc_data3 ftm2_flt0 d6 ptc10 adc1_se6b adc1_se6b ptc10 i2c1_scl ftm3_ch6 i2s0_rx_fs fb_ad5/ nfc_data2 i2s1_mclk a5 ptc11/ llwu_p11 adc1_se7b adc1_se7b ptc11/ llwu_p11 i2c1_sda ftm3_ch7 i2s0_rxd1 fb_rw_b/ nfc_we d7 ptc12 disabled ptc12 uart4_rts_ b fb_ad27 ftm3_flt0 b6 ptc13 disabled ptc13 uart4_cts_ b fb_ad26 c7 ptc14 disabled ptc14 uart4_rx fb_ad25 a6 ptc15 disabled ptc15 uart4_tx fb_ad24 c4 vdd vdd vdd a7 ptc16 disabled ptc16 can1_rx uart3_rx enet0_1588_ tmr0 fb_cs5_b/ fb_tsiz1/ fb_be23_16_ b nfc_rb b7 ptc17 disabled ptc17 can1_tx uart3_tx enet0_1588_ tmr1 fb_cs4_b/ fb_tsiz0/ fb_be31_24_ b nfc_ce0_b pinout k61 sub-family, rev. 7, 02/2018 76 nxp semiconductors
143 wlc sp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport c8 ptc18 disabled ptc18 uart3_rts_ b enet0_1588_ tmr2 fb_tbst_b/ fb_cs2_b/ fb_be15_8_b nfc_ce1_b d8 ptc19 disabled ptc19 uart3_cts_ b enet0_1588_ tmr3 fb_cs3_b/ fb_be7_0_b fb_ta_b b8 ptd0/ llwu_p12 disabled ptd0/ llwu_p12 spi0_pcs0 uart2_rts_ b ftm3_ch0 fb_ale/ fb_cs1_b/ fb_ts_b i2s1_rxd1 a8 ptd1 adc0_se5b adc0_se5b ptd1 spi0_sck uart2_cts_ b ftm3_ch1 fb_cs0_b i2s1_rxd0 d9 ptd2/ llwu_p13 disabled ptd2/ llwu_p13 spi0_sout uart2_rx ftm3_ch2 fb_ad4 i2s1_rx_fs c9 ptd3 disabled ptd3 spi0_sin uart2_tx ftm3_ch3 fb_ad3 i2s1_rx_ bclk b9 ptd4/ llwu_p14 disabled ptd4/ llwu_p14 spi0_pcs1 uart0_rts_ b ftm0_ch4 fb_ad2/ nfc_data1 ewm_in a9 ptd5 adc0_se6b adc0_se6b ptd5 spi0_pcs2 uart0_cts_ b/ uart0_col_ b ftm0_ch5 fb_ad1/ nfc_data0 ewm_out_b b10 ptd6/ llwu_p15 adc0_se7b adc0_se7b ptd6/ llwu_p15 spi0_pcs3 uart0_rx ftm0_ch6 fb_ad0 ftm0_flt0 k2 vdd vdd vdd a10 ptd7 disabled ptd7 cmt_iro uart0_tx ftm0_ch7 ftm0_flt1 b2 nc nc nc c3 nc nc nc a2 nc nc nc b3 nc nc nc a1 nc nc nc m1 nc nc nc m2 nc nc nc m3 nc nc nc m4 nc nc nc m5 nc nc nc m6 nc nc nc m7 nc nc nc a12 nc nc nc b12 nc nc nc c12 nc nc nc d12 nc nc nc e12 nc nc nc f12 nc nc nc g12 nc nc nc h12 nc nc nc pinout k61 sub-family, rev. 7, 02/2018 nxp semiconductors 77
143 wlc sp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport j12 nc nc nc k12 nc nc nc l12 nc nc nc m12 nc nc nc 8.3 k61 pinouts the below figure shows the pinout diagram for the devices supported by this document. many signals may be multiplexed onto a single pin. to determine what signals can be used on which pin, see the previous section. 1 a nc b ptc3/ llwu_p7 c ptc1/ llwu_p6 d ptb20 e ptb16 f ptb11 g ptb7 h ptb3 j reset_b k pta19 l pta18 1 m nc 2 nc nc ptc2 ptb21 ptb17 ptb10 ptb6 ptb2 vss vdd vdd 2 nc 3 ptc4/ llwu_p8 nc nc ptc0 ptb18 ptb9 ptb5 ptb1 pta17 pta16 pta15 3 nc 4 ptc8 ptc5/ llwu_p9 vdd ptb23 ptb19 ptb8 ptb4 ptb0/ llwu_p5 pta14 pta13/ llwu_p4 pta12 4 nc 5 ptc11/ llwu_p11 ptc7 ptc6/ llwu_p10 ptb22 vdd vss vdd pta2 pta3 pta4/ llwu_p3 pta5 5 nc 6 ptc15 ptc13 ptc9 ptc10 vss vss pte26 pta1 pta0 pte27 6 nc 7 ptc16 ptc17 ptc14 ptc12 vdd vdd vdd pte25 vref_out/ cmp1_in5/ cmp0_in5/ adc1_se18 dac1_out/ cmp0_in4/ cmp2_in3/ adc1_se23 pte24 7 nc 8 ptd1 ptd0/ llwu_p12 ptc18 ptc19 vss pte9 vregin pga3_dm/ adc3_dm0/ adc2_dm3/ adc1_dm1 pga1_dm/ adc1_dm0/ adc0_dm3 vssa vbat 8 tamper3 9 ptd5 ptd4/ llwu_p14 ptd3 ptd2/ llwu_p13 pte6 pte10 vout33 pga3_dp/ adc3_dp0/ adc2_dp3/ adc1_dp1 pga1_dp/ adc1_dp0/ adc0_dp3 vrefl extal32 9 tamper2 10 ptd7 ptd6/ llwu_p15 pte1/ llwu_p0 pte3 pte7 pte11 usb0_dm pga2_dm/ adc2_dm0/ adc3_dm3/ adc0_dm1 pga0_dm/ adc0_dm0/ adc1_dm3 vrefh xtal32 10 tamper1 11 pte0 pte2/ llwu_p1 pte4/ llwu_p2 pte5 pte8 pte12 usb0_dp pga2_dp/ adc2_dp0/ adc3_dp3/ adc0_dp1 pga0_dp/ adc0_dp0/ adc1_dp3 vdda dac0_out/ cmp1_in3/ adc0_se23 11 tamper0/ rtc_ wakeup_b 12 a nc b nc c nc d nc e nc f nc g nc h nc j nc k nc l nc 12 m nc figure 41. k61 143 wlcsp pinout diagram pinout k61 sub-family, rev. 7, 02/2018 78 nxp semiconductors
9 revision history the following table provides a revision history for this document. table 59. revision history rev. no. date substantial changes 3 3/2012 initial public release 4 10/2012 replaced tbds throughout. 5 10/2013 changes for 4n96b mask set: ? min vdd operating requirement specification updated to support operation down to 1.71v. new specifications: ? updated vdd_ddr min specification. ? added vodpu specification. ? removed ioz, ioz_ddr, and ioz_tamper hi-z leakage specfications. they have been replaced by new iina, iind, and zind specifications. ? fpll_ref_acc specification has been added. ? i 2 c module was previously covered by the general switching specifications. to provide more detail on i 2 c operation a dedicated inter-integrated circuit interface (i 2 c) timing section has been added. modified specifications: ? vref_ddr max spec has been updated. ? tpor spec has been split into two specifications based on vdd slew rate. ? trd1allx and trd1alln max have been updated. ? 16-bit adc temp sensor slope and temp sensor voltage (vtemp25) have been modified. the typical values that were listed previously have been updated, and min and max specifications have been added. corrections: ? some versions of the datasheets listed incorrect clock mode information in the "diagram: typical idd_run operating behavior section." these errors have been corrected. ? fintf_ft specification was previously shown as a max value. it has been corrected to be shown as a typical value as originally intended. ? corrected ddr write and read timing diagrams to show the correct location of the tcmv specification. ? sdhc peripheral 50mhz high speed mode options were left out of the last datasheet. these have been added to the sdhc specifications section. 6 09/2015 ? updated the footnotes of thermal attributes table ? removed power sequencing section ? added footnote to ambient temperature specification of thermal operating requirements ? removed "usb hs/ls/fs on-the-go controller with on-chip high speed transceiver" from features section ? updated terminology and guidelines section ? updated the footnotes and the values of power consumption operating behaviors table ? added notes in usb electrical specification section ? updated i2c timing table table continues on the next page... revision history k61 sub-family, rev. 7, 02/2018 nxp semiconductors 79
table 59. revision history (continued) rev. no. date substantial changes 7 02/2018 ? updated maximum sdhc frequency in sdhc specifications ? added mdio serial management timing specifications section in ethernet switching specifications revision history k61 sub-family, rev. 7, 02/2018 80 nxp semiconductors
how to reach us: home page: nxp.com web support: nxp.com/support information in this document is provided solely to enable system and software implementers to use nxp products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. nxp reserves the right to make changes without further notice to any products herein. nxp makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does nxp assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. typical parameters that may be provided in nxp data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. all operating parameters, including typicals, must be validated for each customer application by customer's technical experts. nxp does not convey any license under its patent rights nor the rights of others. nxp sells products pursuant to standard terms and conditions of sale, which can be found at the following address: nxp.com/salestermsandconditions . nxp, the nxp logo,nxp secure connections for a smarter world, freescale, the freescale logo, the energy efficient solutions logo, and kinetis are trademarks of nxp b.v. all other product or service names are the property of their respective owners. arm and cortex are registered trademarks of arm limited (or its subsidiaries) in the eu and/or elsewhere. all rights reserved. ? 2012C2018 nxp b.v. document number k61p143m120sf3 revision 7, 02/2018

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